/home/travis/build/MoarVM/MoarVM/src/core/ops.c
Line | Count | Source (jump to first uncovered line) |
1 | | #include "moar.h" |
2 | | /* This file is generated from src/core/oplist by tools/update_ops.p6. */ |
3 | | static const MVMOpInfo MVM_op_infos[] = { |
4 | | { |
5 | | MVM_OP_no_op, |
6 | | "no_op", |
7 | | " ", |
8 | | 0, |
9 | | 0, |
10 | | 0, |
11 | | 0, |
12 | | 0, |
13 | | 0, |
14 | | 0, |
15 | | }, |
16 | | { |
17 | | MVM_OP_const_i8, |
18 | | "const_i8", |
19 | | " ", |
20 | | 2, |
21 | | 1, |
22 | | 0, |
23 | | 0, |
24 | | 0, |
25 | | 0, |
26 | | 0, |
27 | | { MVM_operand_write_reg | MVM_operand_int8, MVM_operand_int8 } |
28 | | }, |
29 | | { |
30 | | MVM_OP_const_i16, |
31 | | "const_i16", |
32 | | " ", |
33 | | 2, |
34 | | 1, |
35 | | 0, |
36 | | 0, |
37 | | 0, |
38 | | 0, |
39 | | 0, |
40 | | { MVM_operand_write_reg | MVM_operand_int16, MVM_operand_int16 } |
41 | | }, |
42 | | { |
43 | | MVM_OP_const_i32, |
44 | | "const_i32", |
45 | | " ", |
46 | | 2, |
47 | | 1, |
48 | | 0, |
49 | | 0, |
50 | | 0, |
51 | | 0, |
52 | | 0, |
53 | | { MVM_operand_write_reg | MVM_operand_int32, MVM_operand_int32 } |
54 | | }, |
55 | | { |
56 | | MVM_OP_const_i64, |
57 | | "const_i64", |
58 | | " ", |
59 | | 2, |
60 | | 1, |
61 | | 0, |
62 | | 0, |
63 | | 0, |
64 | | 0, |
65 | | 0, |
66 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_int64 } |
67 | | }, |
68 | | { |
69 | | MVM_OP_const_n32, |
70 | | "const_n32", |
71 | | " ", |
72 | | 2, |
73 | | 1, |
74 | | 0, |
75 | | 0, |
76 | | 0, |
77 | | 0, |
78 | | 0, |
79 | | { MVM_operand_write_reg | MVM_operand_num32, MVM_operand_num32 } |
80 | | }, |
81 | | { |
82 | | MVM_OP_const_n64, |
83 | | "const_n64", |
84 | | " ", |
85 | | 2, |
86 | | 1, |
87 | | 0, |
88 | | 0, |
89 | | 0, |
90 | | 0, |
91 | | 0, |
92 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_num64 } |
93 | | }, |
94 | | { |
95 | | MVM_OP_const_s, |
96 | | "const_s", |
97 | | " ", |
98 | | 2, |
99 | | 1, |
100 | | 0, |
101 | | 0, |
102 | | 0, |
103 | | 0, |
104 | | 0, |
105 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_str } |
106 | | }, |
107 | | { |
108 | | MVM_OP_set, |
109 | | "set", |
110 | | " ", |
111 | | 2, |
112 | | 1, |
113 | | 0, |
114 | | 0, |
115 | | 0, |
116 | | 0, |
117 | | 0, |
118 | | { MVM_operand_write_reg | MVM_operand_type_var, MVM_operand_read_reg | MVM_operand_type_var } |
119 | | }, |
120 | | { |
121 | | MVM_OP_extend_u8, |
122 | | "extend_u8", |
123 | | " ", |
124 | | 2, |
125 | | 1, |
126 | | 0, |
127 | | 0, |
128 | | 0, |
129 | | 0, |
130 | | 0, |
131 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint8 } |
132 | | }, |
133 | | { |
134 | | MVM_OP_extend_u16, |
135 | | "extend_u16", |
136 | | " ", |
137 | | 2, |
138 | | 1, |
139 | | 0, |
140 | | 0, |
141 | | 0, |
142 | | 0, |
143 | | 0, |
144 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint16 } |
145 | | }, |
146 | | { |
147 | | MVM_OP_extend_u32, |
148 | | "extend_u32", |
149 | | " ", |
150 | | 2, |
151 | | 1, |
152 | | 0, |
153 | | 0, |
154 | | 0, |
155 | | 0, |
156 | | 0, |
157 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint32 } |
158 | | }, |
159 | | { |
160 | | MVM_OP_extend_i8, |
161 | | "extend_i8", |
162 | | " ", |
163 | | 2, |
164 | | 1, |
165 | | 0, |
166 | | 0, |
167 | | 0, |
168 | | 0, |
169 | | 0, |
170 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int8 } |
171 | | }, |
172 | | { |
173 | | MVM_OP_extend_i16, |
174 | | "extend_i16", |
175 | | " ", |
176 | | 2, |
177 | | 1, |
178 | | 0, |
179 | | 0, |
180 | | 0, |
181 | | 0, |
182 | | 0, |
183 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int16 } |
184 | | }, |
185 | | { |
186 | | MVM_OP_extend_i32, |
187 | | "extend_i32", |
188 | | " ", |
189 | | 2, |
190 | | 1, |
191 | | 0, |
192 | | 0, |
193 | | 0, |
194 | | 0, |
195 | | 0, |
196 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int32 } |
197 | | }, |
198 | | { |
199 | | MVM_OP_trunc_u8, |
200 | | "trunc_u8", |
201 | | " ", |
202 | | 2, |
203 | | 1, |
204 | | 0, |
205 | | 0, |
206 | | 0, |
207 | | 0, |
208 | | 0, |
209 | | { MVM_operand_write_reg | MVM_operand_uint8, MVM_operand_read_reg | MVM_operand_uint64 } |
210 | | }, |
211 | | { |
212 | | MVM_OP_trunc_u16, |
213 | | "trunc_u16", |
214 | | " ", |
215 | | 2, |
216 | | 1, |
217 | | 0, |
218 | | 0, |
219 | | 0, |
220 | | 0, |
221 | | 0, |
222 | | { MVM_operand_write_reg | MVM_operand_uint16, MVM_operand_read_reg | MVM_operand_uint64 } |
223 | | }, |
224 | | { |
225 | | MVM_OP_trunc_u32, |
226 | | "trunc_u32", |
227 | | " ", |
228 | | 2, |
229 | | 1, |
230 | | 0, |
231 | | 0, |
232 | | 0, |
233 | | 0, |
234 | | 0, |
235 | | { MVM_operand_write_reg | MVM_operand_uint32, MVM_operand_read_reg | MVM_operand_uint64 } |
236 | | }, |
237 | | { |
238 | | MVM_OP_trunc_i8, |
239 | | "trunc_i8", |
240 | | " ", |
241 | | 2, |
242 | | 1, |
243 | | 0, |
244 | | 0, |
245 | | 0, |
246 | | 0, |
247 | | 0, |
248 | | { MVM_operand_write_reg | MVM_operand_int8, MVM_operand_read_reg | MVM_operand_int64 } |
249 | | }, |
250 | | { |
251 | | MVM_OP_trunc_i16, |
252 | | "trunc_i16", |
253 | | " ", |
254 | | 2, |
255 | | 1, |
256 | | 0, |
257 | | 0, |
258 | | 0, |
259 | | 0, |
260 | | 0, |
261 | | { MVM_operand_write_reg | MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
262 | | }, |
263 | | { |
264 | | MVM_OP_trunc_i32, |
265 | | "trunc_i32", |
266 | | " ", |
267 | | 2, |
268 | | 1, |
269 | | 0, |
270 | | 0, |
271 | | 0, |
272 | | 0, |
273 | | 0, |
274 | | { MVM_operand_write_reg | MVM_operand_int32, MVM_operand_read_reg | MVM_operand_int64 } |
275 | | }, |
276 | | { |
277 | | MVM_OP_extend_n32, |
278 | | "extend_n32", |
279 | | " ", |
280 | | 2, |
281 | | 1, |
282 | | 0, |
283 | | 0, |
284 | | 0, |
285 | | 0, |
286 | | 0, |
287 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num32 } |
288 | | }, |
289 | | { |
290 | | MVM_OP_trunc_n32, |
291 | | "trunc_n32", |
292 | | " ", |
293 | | 2, |
294 | | 1, |
295 | | 0, |
296 | | 0, |
297 | | 0, |
298 | | 0, |
299 | | 0, |
300 | | { MVM_operand_write_reg | MVM_operand_num32, MVM_operand_read_reg | MVM_operand_num64 } |
301 | | }, |
302 | | { |
303 | | MVM_OP_goto, |
304 | | "goto", |
305 | | ".j", |
306 | | 1, |
307 | | 0, |
308 | | 0, |
309 | | 0, |
310 | | 0, |
311 | | 0, |
312 | | 0, |
313 | | { MVM_operand_ins } |
314 | | }, |
315 | | { |
316 | | MVM_OP_if_i, |
317 | | "if_i", |
318 | | " ", |
319 | | 2, |
320 | | 0, |
321 | | 0, |
322 | | 0, |
323 | | 0, |
324 | | 0, |
325 | | 0, |
326 | | { MVM_operand_read_reg | MVM_operand_int64, MVM_operand_ins } |
327 | | }, |
328 | | { |
329 | | MVM_OP_unless_i, |
330 | | "unless_i", |
331 | | " ", |
332 | | 2, |
333 | | 0, |
334 | | 0, |
335 | | 0, |
336 | | 0, |
337 | | 0, |
338 | | 0, |
339 | | { MVM_operand_read_reg | MVM_operand_int64, MVM_operand_ins } |
340 | | }, |
341 | | { |
342 | | MVM_OP_if_n, |
343 | | "if_n", |
344 | | " ", |
345 | | 2, |
346 | | 0, |
347 | | 0, |
348 | | 0, |
349 | | 0, |
350 | | 0, |
351 | | 0, |
352 | | { MVM_operand_read_reg | MVM_operand_num64, MVM_operand_ins } |
353 | | }, |
354 | | { |
355 | | MVM_OP_unless_n, |
356 | | "unless_n", |
357 | | " ", |
358 | | 2, |
359 | | 0, |
360 | | 0, |
361 | | 0, |
362 | | 0, |
363 | | 0, |
364 | | 0, |
365 | | { MVM_operand_read_reg | MVM_operand_num64, MVM_operand_ins } |
366 | | }, |
367 | | { |
368 | | MVM_OP_if_s, |
369 | | "if_s", |
370 | | " ", |
371 | | 2, |
372 | | 0, |
373 | | 0, |
374 | | 0, |
375 | | 0, |
376 | | 0, |
377 | | 0, |
378 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_ins } |
379 | | }, |
380 | | { |
381 | | MVM_OP_unless_s, |
382 | | "unless_s", |
383 | | " ", |
384 | | 2, |
385 | | 0, |
386 | | 0, |
387 | | 0, |
388 | | 0, |
389 | | 0, |
390 | | 0, |
391 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_ins } |
392 | | }, |
393 | | { |
394 | | MVM_OP_if_s0, |
395 | | "if_s0", |
396 | | " ", |
397 | | 2, |
398 | | 0, |
399 | | 0, |
400 | | 0, |
401 | | 0, |
402 | | 0, |
403 | | 0, |
404 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_ins } |
405 | | }, |
406 | | { |
407 | | MVM_OP_unless_s0, |
408 | | "unless_s0", |
409 | | " ", |
410 | | 2, |
411 | | 0, |
412 | | 0, |
413 | | 0, |
414 | | 0, |
415 | | 0, |
416 | | 0, |
417 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_ins } |
418 | | }, |
419 | | { |
420 | | MVM_OP_if_o, |
421 | | "if_o", |
422 | | " ", |
423 | | 2, |
424 | | 0, |
425 | | 0, |
426 | | 0, |
427 | | 0, |
428 | | 1, |
429 | | 0, |
430 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_ins } |
431 | | }, |
432 | | { |
433 | | MVM_OP_unless_o, |
434 | | "unless_o", |
435 | | " ", |
436 | | 2, |
437 | | 0, |
438 | | 0, |
439 | | 0, |
440 | | 0, |
441 | | 1, |
442 | | 0, |
443 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_ins } |
444 | | }, |
445 | | { |
446 | | MVM_OP_jumplist, |
447 | | "jumplist", |
448 | | ":j", |
449 | | 2, |
450 | | 0, |
451 | | 0, |
452 | | 0, |
453 | | 0, |
454 | | 0, |
455 | | 0, |
456 | | { MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
457 | | }, |
458 | | { |
459 | | MVM_OP_getlex, |
460 | | "getlex", |
461 | | " ", |
462 | | 2, |
463 | | 1, |
464 | | 1, |
465 | | 1, |
466 | | 0, |
467 | | 0, |
468 | | 0, |
469 | | { MVM_operand_write_reg | MVM_operand_type_var, MVM_operand_read_lex | MVM_operand_type_var } |
470 | | }, |
471 | | { |
472 | | MVM_OP_bindlex, |
473 | | "bindlex", |
474 | | " ", |
475 | | 2, |
476 | | 0, |
477 | | 0, |
478 | | 0, |
479 | | 0, |
480 | | 0, |
481 | | 0, |
482 | | { MVM_operand_write_lex | MVM_operand_type_var, MVM_operand_read_reg | MVM_operand_type_var } |
483 | | }, |
484 | | { |
485 | | MVM_OP_getlex_ni, |
486 | | "getlex_ni", |
487 | | " ", |
488 | | 2, |
489 | | 1, |
490 | | 0, |
491 | | 0, |
492 | | 1, |
493 | | 0, |
494 | | 0, |
495 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_str } |
496 | | }, |
497 | | { |
498 | | MVM_OP_getlex_nn, |
499 | | "getlex_nn", |
500 | | " ", |
501 | | 2, |
502 | | 1, |
503 | | 0, |
504 | | 0, |
505 | | 1, |
506 | | 0, |
507 | | 0, |
508 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_str } |
509 | | }, |
510 | | { |
511 | | MVM_OP_getlex_ns, |
512 | | "getlex_ns", |
513 | | " ", |
514 | | 2, |
515 | | 1, |
516 | | 0, |
517 | | 0, |
518 | | 1, |
519 | | 0, |
520 | | 0, |
521 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_str } |
522 | | }, |
523 | | { |
524 | | MVM_OP_getlex_no, |
525 | | "getlex_no", |
526 | | " ", |
527 | | 2, |
528 | | 1, |
529 | | 1, |
530 | | 1, |
531 | | 1, |
532 | | 0, |
533 | | 0, |
534 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
535 | | }, |
536 | | { |
537 | | MVM_OP_bindlex_ni, |
538 | | "bindlex_ni", |
539 | | " ", |
540 | | 2, |
541 | | 0, |
542 | | 0, |
543 | | 0, |
544 | | 1, |
545 | | 0, |
546 | | 0, |
547 | | { MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
548 | | }, |
549 | | { |
550 | | MVM_OP_bindlex_nn, |
551 | | "bindlex_nn", |
552 | | " ", |
553 | | 2, |
554 | | 0, |
555 | | 0, |
556 | | 0, |
557 | | 1, |
558 | | 0, |
559 | | 0, |
560 | | { MVM_operand_str, MVM_operand_read_reg | MVM_operand_num64 } |
561 | | }, |
562 | | { |
563 | | MVM_OP_bindlex_ns, |
564 | | "bindlex_ns", |
565 | | " ", |
566 | | 2, |
567 | | 0, |
568 | | 0, |
569 | | 0, |
570 | | 1, |
571 | | 0, |
572 | | 0, |
573 | | { MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
574 | | }, |
575 | | { |
576 | | MVM_OP_bindlex_no, |
577 | | "bindlex_no", |
578 | | " ", |
579 | | 2, |
580 | | 0, |
581 | | 0, |
582 | | 0, |
583 | | 1, |
584 | | 0, |
585 | | 0, |
586 | | { MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
587 | | }, |
588 | | { |
589 | | MVM_OP_getlex_ng, |
590 | | "getlex_ng", |
591 | | " ", |
592 | | 2, |
593 | | 1, |
594 | | 0, |
595 | | 0, |
596 | | 1, |
597 | | 0, |
598 | | 1, |
599 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
600 | | }, |
601 | | { |
602 | | MVM_OP_bindlex_ng, |
603 | | "bindlex_ng", |
604 | | " ", |
605 | | 2, |
606 | | 0, |
607 | | 0, |
608 | | 0, |
609 | | 1, |
610 | | 0, |
611 | | 1, |
612 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
613 | | }, |
614 | | { |
615 | | MVM_OP_getdynlex, |
616 | | "getdynlex", |
617 | | " ", |
618 | | 2, |
619 | | 1, |
620 | | 0, |
621 | | 0, |
622 | | 1, |
623 | | 0, |
624 | | 1, |
625 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
626 | | }, |
627 | | { |
628 | | MVM_OP_binddynlex, |
629 | | "binddynlex", |
630 | | " ", |
631 | | 2, |
632 | | 0, |
633 | | 0, |
634 | | 0, |
635 | | 1, |
636 | | 0, |
637 | | 0, |
638 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
639 | | }, |
640 | | { |
641 | | MVM_OP_setlexvalue, |
642 | | "setlexvalue", |
643 | | " ", |
644 | | 4, |
645 | | 0, |
646 | | 0, |
647 | | 0, |
648 | | 0, |
649 | | 0, |
650 | | 0, |
651 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
652 | | }, |
653 | | { |
654 | | MVM_OP_lexprimspec, |
655 | | "lexprimspec", |
656 | | " ", |
657 | | 3, |
658 | | 1, |
659 | | 0, |
660 | | 0, |
661 | | 0, |
662 | | 0, |
663 | | 0, |
664 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
665 | | }, |
666 | | { |
667 | | MVM_OP_return_i, |
668 | | "return_i", |
669 | | ".r", |
670 | | 1, |
671 | | 0, |
672 | | 0, |
673 | | 0, |
674 | | 0, |
675 | | 0, |
676 | | 1, |
677 | | { MVM_operand_read_reg | MVM_operand_int64 } |
678 | | }, |
679 | | { |
680 | | MVM_OP_return_n, |
681 | | "return_n", |
682 | | ".r", |
683 | | 1, |
684 | | 0, |
685 | | 0, |
686 | | 0, |
687 | | 0, |
688 | | 0, |
689 | | 1, |
690 | | { MVM_operand_read_reg | MVM_operand_num64 } |
691 | | }, |
692 | | { |
693 | | MVM_OP_return_s, |
694 | | "return_s", |
695 | | ".r", |
696 | | 1, |
697 | | 0, |
698 | | 0, |
699 | | 0, |
700 | | 0, |
701 | | 0, |
702 | | 1, |
703 | | { MVM_operand_read_reg | MVM_operand_str } |
704 | | }, |
705 | | { |
706 | | MVM_OP_return_o, |
707 | | "return_o", |
708 | | ".r", |
709 | | 1, |
710 | | 0, |
711 | | 0, |
712 | | 0, |
713 | | 0, |
714 | | 0, |
715 | | 0, |
716 | | { MVM_operand_read_reg | MVM_operand_obj } |
717 | | }, |
718 | | { |
719 | | MVM_OP_return, |
720 | | "return", |
721 | | ".r", |
722 | | 0, |
723 | | 0, |
724 | | 0, |
725 | | 0, |
726 | | 0, |
727 | | 0, |
728 | | 0, |
729 | | }, |
730 | | { |
731 | | MVM_OP_eq_i, |
732 | | "eq_i", |
733 | | " ", |
734 | | 3, |
735 | | 1, |
736 | | 0, |
737 | | 0, |
738 | | 0, |
739 | | 0, |
740 | | 0, |
741 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
742 | | }, |
743 | | { |
744 | | MVM_OP_ne_i, |
745 | | "ne_i", |
746 | | " ", |
747 | | 3, |
748 | | 1, |
749 | | 0, |
750 | | 0, |
751 | | 0, |
752 | | 0, |
753 | | 0, |
754 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
755 | | }, |
756 | | { |
757 | | MVM_OP_lt_i, |
758 | | "lt_i", |
759 | | " ", |
760 | | 3, |
761 | | 1, |
762 | | 0, |
763 | | 0, |
764 | | 0, |
765 | | 0, |
766 | | 0, |
767 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
768 | | }, |
769 | | { |
770 | | MVM_OP_le_i, |
771 | | "le_i", |
772 | | " ", |
773 | | 3, |
774 | | 1, |
775 | | 0, |
776 | | 0, |
777 | | 0, |
778 | | 0, |
779 | | 0, |
780 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
781 | | }, |
782 | | { |
783 | | MVM_OP_gt_i, |
784 | | "gt_i", |
785 | | " ", |
786 | | 3, |
787 | | 1, |
788 | | 0, |
789 | | 0, |
790 | | 0, |
791 | | 0, |
792 | | 0, |
793 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
794 | | }, |
795 | | { |
796 | | MVM_OP_ge_i, |
797 | | "ge_i", |
798 | | " ", |
799 | | 3, |
800 | | 1, |
801 | | 0, |
802 | | 0, |
803 | | 0, |
804 | | 0, |
805 | | 0, |
806 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
807 | | }, |
808 | | { |
809 | | MVM_OP_cmp_i, |
810 | | "cmp_i", |
811 | | " ", |
812 | | 3, |
813 | | 1, |
814 | | 0, |
815 | | 0, |
816 | | 0, |
817 | | 0, |
818 | | 0, |
819 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
820 | | }, |
821 | | { |
822 | | MVM_OP_add_i, |
823 | | "add_i", |
824 | | " ", |
825 | | 3, |
826 | | 1, |
827 | | 0, |
828 | | 0, |
829 | | 0, |
830 | | 0, |
831 | | 0, |
832 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
833 | | }, |
834 | | { |
835 | | MVM_OP_sub_i, |
836 | | "sub_i", |
837 | | " ", |
838 | | 3, |
839 | | 1, |
840 | | 0, |
841 | | 0, |
842 | | 0, |
843 | | 0, |
844 | | 0, |
845 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
846 | | }, |
847 | | { |
848 | | MVM_OP_mul_i, |
849 | | "mul_i", |
850 | | " ", |
851 | | 3, |
852 | | 1, |
853 | | 0, |
854 | | 0, |
855 | | 0, |
856 | | 0, |
857 | | 0, |
858 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
859 | | }, |
860 | | { |
861 | | MVM_OP_div_i, |
862 | | "div_i", |
863 | | " ", |
864 | | 3, |
865 | | 1, |
866 | | 0, |
867 | | 0, |
868 | | 0, |
869 | | 0, |
870 | | 0, |
871 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
872 | | }, |
873 | | { |
874 | | MVM_OP_div_u, |
875 | | "div_u", |
876 | | " ", |
877 | | 3, |
878 | | 1, |
879 | | 0, |
880 | | 0, |
881 | | 0, |
882 | | 0, |
883 | | 0, |
884 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint64 } |
885 | | }, |
886 | | { |
887 | | MVM_OP_mod_i, |
888 | | "mod_i", |
889 | | " ", |
890 | | 3, |
891 | | 1, |
892 | | 0, |
893 | | 0, |
894 | | 0, |
895 | | 0, |
896 | | 0, |
897 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
898 | | }, |
899 | | { |
900 | | MVM_OP_mod_u, |
901 | | "mod_u", |
902 | | " ", |
903 | | 3, |
904 | | 1, |
905 | | 0, |
906 | | 0, |
907 | | 0, |
908 | | 0, |
909 | | 0, |
910 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_uint64 } |
911 | | }, |
912 | | { |
913 | | MVM_OP_neg_i, |
914 | | "neg_i", |
915 | | " ", |
916 | | 2, |
917 | | 1, |
918 | | 0, |
919 | | 0, |
920 | | 0, |
921 | | 0, |
922 | | 0, |
923 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
924 | | }, |
925 | | { |
926 | | MVM_OP_abs_i, |
927 | | "abs_i", |
928 | | " ", |
929 | | 2, |
930 | | 1, |
931 | | 0, |
932 | | 0, |
933 | | 0, |
934 | | 0, |
935 | | 0, |
936 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
937 | | }, |
938 | | { |
939 | | MVM_OP_inc_i, |
940 | | "inc_i", |
941 | | " ", |
942 | | 1, |
943 | | 0, |
944 | | 0, |
945 | | 0, |
946 | | 0, |
947 | | 0, |
948 | | 0, |
949 | | { MVM_operand_write_reg | MVM_operand_int64 } |
950 | | }, |
951 | | { |
952 | | MVM_OP_inc_u, |
953 | | "inc_u", |
954 | | " ", |
955 | | 1, |
956 | | 0, |
957 | | 0, |
958 | | 0, |
959 | | 0, |
960 | | 0, |
961 | | 0, |
962 | | { MVM_operand_write_reg | MVM_operand_uint64 } |
963 | | }, |
964 | | { |
965 | | MVM_OP_dec_i, |
966 | | "dec_i", |
967 | | " ", |
968 | | 1, |
969 | | 0, |
970 | | 0, |
971 | | 0, |
972 | | 0, |
973 | | 0, |
974 | | 0, |
975 | | { MVM_operand_write_reg | MVM_operand_int64 } |
976 | | }, |
977 | | { |
978 | | MVM_OP_dec_u, |
979 | | "dec_u", |
980 | | " ", |
981 | | 1, |
982 | | 0, |
983 | | 0, |
984 | | 0, |
985 | | 0, |
986 | | 0, |
987 | | 0, |
988 | | { MVM_operand_write_reg | MVM_operand_uint64 } |
989 | | }, |
990 | | { |
991 | | MVM_OP_band_i, |
992 | | "band_i", |
993 | | " ", |
994 | | 3, |
995 | | 1, |
996 | | 0, |
997 | | 0, |
998 | | 0, |
999 | | 0, |
1000 | | 0, |
1001 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1002 | | }, |
1003 | | { |
1004 | | MVM_OP_bor_i, |
1005 | | "bor_i", |
1006 | | " ", |
1007 | | 3, |
1008 | | 1, |
1009 | | 0, |
1010 | | 0, |
1011 | | 0, |
1012 | | 0, |
1013 | | 0, |
1014 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1015 | | }, |
1016 | | { |
1017 | | MVM_OP_bxor_i, |
1018 | | "bxor_i", |
1019 | | " ", |
1020 | | 3, |
1021 | | 1, |
1022 | | 0, |
1023 | | 0, |
1024 | | 0, |
1025 | | 0, |
1026 | | 0, |
1027 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1028 | | }, |
1029 | | { |
1030 | | MVM_OP_bnot_i, |
1031 | | "bnot_i", |
1032 | | " ", |
1033 | | 2, |
1034 | | 1, |
1035 | | 0, |
1036 | | 0, |
1037 | | 0, |
1038 | | 0, |
1039 | | 0, |
1040 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1041 | | }, |
1042 | | { |
1043 | | MVM_OP_blshift_i, |
1044 | | "blshift_i", |
1045 | | " ", |
1046 | | 3, |
1047 | | 1, |
1048 | | 0, |
1049 | | 0, |
1050 | | 0, |
1051 | | 0, |
1052 | | 0, |
1053 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1054 | | }, |
1055 | | { |
1056 | | MVM_OP_brshift_i, |
1057 | | "brshift_i", |
1058 | | " ", |
1059 | | 3, |
1060 | | 1, |
1061 | | 0, |
1062 | | 0, |
1063 | | 0, |
1064 | | 0, |
1065 | | 0, |
1066 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1067 | | }, |
1068 | | { |
1069 | | MVM_OP_pow_i, |
1070 | | "pow_i", |
1071 | | " ", |
1072 | | 3, |
1073 | | 1, |
1074 | | 0, |
1075 | | 0, |
1076 | | 0, |
1077 | | 0, |
1078 | | 0, |
1079 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1080 | | }, |
1081 | | { |
1082 | | MVM_OP_not_i, |
1083 | | "not_i", |
1084 | | " ", |
1085 | | 2, |
1086 | | 1, |
1087 | | 0, |
1088 | | 0, |
1089 | | 0, |
1090 | | 0, |
1091 | | 0, |
1092 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1093 | | }, |
1094 | | { |
1095 | | MVM_OP_gcd_i, |
1096 | | "gcd_i", |
1097 | | " ", |
1098 | | 3, |
1099 | | 1, |
1100 | | 0, |
1101 | | 0, |
1102 | | 0, |
1103 | | 0, |
1104 | | 0, |
1105 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1106 | | }, |
1107 | | { |
1108 | | MVM_OP_lcm_i, |
1109 | | "lcm_i", |
1110 | | " ", |
1111 | | 3, |
1112 | | 1, |
1113 | | 0, |
1114 | | 0, |
1115 | | 0, |
1116 | | 0, |
1117 | | 0, |
1118 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
1119 | | }, |
1120 | | { |
1121 | | MVM_OP_eq_n, |
1122 | | "eq_n", |
1123 | | " ", |
1124 | | 3, |
1125 | | 1, |
1126 | | 0, |
1127 | | 0, |
1128 | | 0, |
1129 | | 0, |
1130 | | 0, |
1131 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1132 | | }, |
1133 | | { |
1134 | | MVM_OP_ne_n, |
1135 | | "ne_n", |
1136 | | " ", |
1137 | | 3, |
1138 | | 1, |
1139 | | 0, |
1140 | | 0, |
1141 | | 0, |
1142 | | 0, |
1143 | | 0, |
1144 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1145 | | }, |
1146 | | { |
1147 | | MVM_OP_lt_n, |
1148 | | "lt_n", |
1149 | | " ", |
1150 | | 3, |
1151 | | 1, |
1152 | | 0, |
1153 | | 0, |
1154 | | 0, |
1155 | | 0, |
1156 | | 0, |
1157 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1158 | | }, |
1159 | | { |
1160 | | MVM_OP_le_n, |
1161 | | "le_n", |
1162 | | " ", |
1163 | | 3, |
1164 | | 1, |
1165 | | 0, |
1166 | | 0, |
1167 | | 0, |
1168 | | 0, |
1169 | | 0, |
1170 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1171 | | }, |
1172 | | { |
1173 | | MVM_OP_gt_n, |
1174 | | "gt_n", |
1175 | | " ", |
1176 | | 3, |
1177 | | 1, |
1178 | | 0, |
1179 | | 0, |
1180 | | 0, |
1181 | | 0, |
1182 | | 0, |
1183 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1184 | | }, |
1185 | | { |
1186 | | MVM_OP_ge_n, |
1187 | | "ge_n", |
1188 | | " ", |
1189 | | 3, |
1190 | | 1, |
1191 | | 0, |
1192 | | 0, |
1193 | | 0, |
1194 | | 0, |
1195 | | 0, |
1196 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1197 | | }, |
1198 | | { |
1199 | | MVM_OP_cmp_n, |
1200 | | "cmp_n", |
1201 | | " ", |
1202 | | 3, |
1203 | | 1, |
1204 | | 0, |
1205 | | 0, |
1206 | | 0, |
1207 | | 0, |
1208 | | 0, |
1209 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1210 | | }, |
1211 | | { |
1212 | | MVM_OP_add_n, |
1213 | | "add_n", |
1214 | | " ", |
1215 | | 3, |
1216 | | 1, |
1217 | | 0, |
1218 | | 0, |
1219 | | 0, |
1220 | | 0, |
1221 | | 0, |
1222 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1223 | | }, |
1224 | | { |
1225 | | MVM_OP_sub_n, |
1226 | | "sub_n", |
1227 | | " ", |
1228 | | 3, |
1229 | | 1, |
1230 | | 0, |
1231 | | 0, |
1232 | | 0, |
1233 | | 0, |
1234 | | 0, |
1235 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1236 | | }, |
1237 | | { |
1238 | | MVM_OP_mul_n, |
1239 | | "mul_n", |
1240 | | " ", |
1241 | | 3, |
1242 | | 1, |
1243 | | 0, |
1244 | | 0, |
1245 | | 0, |
1246 | | 0, |
1247 | | 0, |
1248 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1249 | | }, |
1250 | | { |
1251 | | MVM_OP_div_n, |
1252 | | "div_n", |
1253 | | " ", |
1254 | | 3, |
1255 | | 1, |
1256 | | 0, |
1257 | | 0, |
1258 | | 0, |
1259 | | 0, |
1260 | | 0, |
1261 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1262 | | }, |
1263 | | { |
1264 | | MVM_OP_mod_n, |
1265 | | "mod_n", |
1266 | | " ", |
1267 | | 3, |
1268 | | 1, |
1269 | | 0, |
1270 | | 0, |
1271 | | 0, |
1272 | | 0, |
1273 | | 0, |
1274 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1275 | | }, |
1276 | | { |
1277 | | MVM_OP_neg_n, |
1278 | | "neg_n", |
1279 | | " ", |
1280 | | 2, |
1281 | | 1, |
1282 | | 0, |
1283 | | 0, |
1284 | | 0, |
1285 | | 0, |
1286 | | 0, |
1287 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1288 | | }, |
1289 | | { |
1290 | | MVM_OP_abs_n, |
1291 | | "abs_n", |
1292 | | " ", |
1293 | | 2, |
1294 | | 1, |
1295 | | 0, |
1296 | | 0, |
1297 | | 0, |
1298 | | 0, |
1299 | | 0, |
1300 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1301 | | }, |
1302 | | { |
1303 | | MVM_OP_pow_n, |
1304 | | "pow_n", |
1305 | | " ", |
1306 | | 3, |
1307 | | 1, |
1308 | | 0, |
1309 | | 0, |
1310 | | 0, |
1311 | | 0, |
1312 | | 0, |
1313 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1314 | | }, |
1315 | | { |
1316 | | MVM_OP_ceil_n, |
1317 | | "ceil_n", |
1318 | | " ", |
1319 | | 2, |
1320 | | 1, |
1321 | | 0, |
1322 | | 0, |
1323 | | 0, |
1324 | | 0, |
1325 | | 0, |
1326 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1327 | | }, |
1328 | | { |
1329 | | MVM_OP_floor_n, |
1330 | | "floor_n", |
1331 | | " ", |
1332 | | 2, |
1333 | | 1, |
1334 | | 0, |
1335 | | 0, |
1336 | | 0, |
1337 | | 0, |
1338 | | 0, |
1339 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1340 | | }, |
1341 | | { |
1342 | | MVM_OP_sin_n, |
1343 | | "sin_n", |
1344 | | " ", |
1345 | | 2, |
1346 | | 1, |
1347 | | 0, |
1348 | | 0, |
1349 | | 0, |
1350 | | 0, |
1351 | | 0, |
1352 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1353 | | }, |
1354 | | { |
1355 | | MVM_OP_asin_n, |
1356 | | "asin_n", |
1357 | | " ", |
1358 | | 2, |
1359 | | 1, |
1360 | | 0, |
1361 | | 0, |
1362 | | 0, |
1363 | | 0, |
1364 | | 0, |
1365 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1366 | | }, |
1367 | | { |
1368 | | MVM_OP_cos_n, |
1369 | | "cos_n", |
1370 | | " ", |
1371 | | 2, |
1372 | | 1, |
1373 | | 0, |
1374 | | 0, |
1375 | | 0, |
1376 | | 0, |
1377 | | 0, |
1378 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1379 | | }, |
1380 | | { |
1381 | | MVM_OP_acos_n, |
1382 | | "acos_n", |
1383 | | " ", |
1384 | | 2, |
1385 | | 1, |
1386 | | 0, |
1387 | | 0, |
1388 | | 0, |
1389 | | 0, |
1390 | | 0, |
1391 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1392 | | }, |
1393 | | { |
1394 | | MVM_OP_tan_n, |
1395 | | "tan_n", |
1396 | | " ", |
1397 | | 2, |
1398 | | 1, |
1399 | | 0, |
1400 | | 0, |
1401 | | 0, |
1402 | | 0, |
1403 | | 0, |
1404 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1405 | | }, |
1406 | | { |
1407 | | MVM_OP_atan_n, |
1408 | | "atan_n", |
1409 | | " ", |
1410 | | 2, |
1411 | | 1, |
1412 | | 0, |
1413 | | 0, |
1414 | | 0, |
1415 | | 0, |
1416 | | 0, |
1417 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1418 | | }, |
1419 | | { |
1420 | | MVM_OP_atan2_n, |
1421 | | "atan2_n", |
1422 | | " ", |
1423 | | 3, |
1424 | | 1, |
1425 | | 0, |
1426 | | 0, |
1427 | | 0, |
1428 | | 0, |
1429 | | 0, |
1430 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1431 | | }, |
1432 | | { |
1433 | | MVM_OP_sec_n, |
1434 | | "sec_n", |
1435 | | " ", |
1436 | | 2, |
1437 | | 1, |
1438 | | 0, |
1439 | | 0, |
1440 | | 0, |
1441 | | 0, |
1442 | | 0, |
1443 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1444 | | }, |
1445 | | { |
1446 | | MVM_OP_asec_n, |
1447 | | "asec_n", |
1448 | | " ", |
1449 | | 2, |
1450 | | 1, |
1451 | | 0, |
1452 | | 0, |
1453 | | 0, |
1454 | | 0, |
1455 | | 0, |
1456 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1457 | | }, |
1458 | | { |
1459 | | MVM_OP_sinh_n, |
1460 | | "sinh_n", |
1461 | | " ", |
1462 | | 2, |
1463 | | 1, |
1464 | | 0, |
1465 | | 0, |
1466 | | 0, |
1467 | | 0, |
1468 | | 0, |
1469 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1470 | | }, |
1471 | | { |
1472 | | MVM_OP_cosh_n, |
1473 | | "cosh_n", |
1474 | | " ", |
1475 | | 2, |
1476 | | 1, |
1477 | | 0, |
1478 | | 0, |
1479 | | 0, |
1480 | | 0, |
1481 | | 0, |
1482 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1483 | | }, |
1484 | | { |
1485 | | MVM_OP_tanh_n, |
1486 | | "tanh_n", |
1487 | | " ", |
1488 | | 2, |
1489 | | 1, |
1490 | | 0, |
1491 | | 0, |
1492 | | 0, |
1493 | | 0, |
1494 | | 0, |
1495 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1496 | | }, |
1497 | | { |
1498 | | MVM_OP_sech_n, |
1499 | | "sech_n", |
1500 | | " ", |
1501 | | 2, |
1502 | | 1, |
1503 | | 0, |
1504 | | 0, |
1505 | | 0, |
1506 | | 0, |
1507 | | 0, |
1508 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1509 | | }, |
1510 | | { |
1511 | | MVM_OP_sqrt_n, |
1512 | | "sqrt_n", |
1513 | | " ", |
1514 | | 2, |
1515 | | 1, |
1516 | | 0, |
1517 | | 0, |
1518 | | 0, |
1519 | | 0, |
1520 | | 0, |
1521 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1522 | | }, |
1523 | | { |
1524 | | MVM_OP_log_n, |
1525 | | "log_n", |
1526 | | " ", |
1527 | | 2, |
1528 | | 1, |
1529 | | 0, |
1530 | | 0, |
1531 | | 0, |
1532 | | 0, |
1533 | | 0, |
1534 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1535 | | }, |
1536 | | { |
1537 | | MVM_OP_exp_n, |
1538 | | "exp_n", |
1539 | | " ", |
1540 | | 2, |
1541 | | 1, |
1542 | | 0, |
1543 | | 0, |
1544 | | 0, |
1545 | | 0, |
1546 | | 0, |
1547 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
1548 | | }, |
1549 | | { |
1550 | | MVM_OP_coerce_in, |
1551 | | "coerce_in", |
1552 | | " ", |
1553 | | 2, |
1554 | | 1, |
1555 | | 0, |
1556 | | 0, |
1557 | | 0, |
1558 | | 0, |
1559 | | 0, |
1560 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_int64 } |
1561 | | }, |
1562 | | { |
1563 | | MVM_OP_coerce_ni, |
1564 | | "coerce_ni", |
1565 | | " ", |
1566 | | 2, |
1567 | | 1, |
1568 | | 0, |
1569 | | 0, |
1570 | | 0, |
1571 | | 0, |
1572 | | 0, |
1573 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64 } |
1574 | | }, |
1575 | | { |
1576 | | MVM_OP_coerce_is, |
1577 | | "coerce_is", |
1578 | | " ", |
1579 | | 2, |
1580 | | 1, |
1581 | | 0, |
1582 | | 0, |
1583 | | 0, |
1584 | | 0, |
1585 | | 0, |
1586 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
1587 | | }, |
1588 | | { |
1589 | | MVM_OP_coerce_ns, |
1590 | | "coerce_ns", |
1591 | | " ", |
1592 | | 2, |
1593 | | 1, |
1594 | | 0, |
1595 | | 0, |
1596 | | 0, |
1597 | | 0, |
1598 | | 0, |
1599 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_num64 } |
1600 | | }, |
1601 | | { |
1602 | | MVM_OP_coerce_si, |
1603 | | "coerce_si", |
1604 | | " ", |
1605 | | 2, |
1606 | | 1, |
1607 | | 0, |
1608 | | 0, |
1609 | | 0, |
1610 | | 0, |
1611 | | 0, |
1612 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
1613 | | }, |
1614 | | { |
1615 | | MVM_OP_coerce_sn, |
1616 | | "coerce_sn", |
1617 | | " ", |
1618 | | 2, |
1619 | | 1, |
1620 | | 0, |
1621 | | 0, |
1622 | | 0, |
1623 | | 0, |
1624 | | 0, |
1625 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_str } |
1626 | | }, |
1627 | | { |
1628 | | MVM_OP_smrt_numify, |
1629 | | "smrt_numify", |
1630 | | " ", |
1631 | | 2, |
1632 | | 1, |
1633 | | 0, |
1634 | | 0, |
1635 | | 0, |
1636 | | 1, |
1637 | | 0, |
1638 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
1639 | | }, |
1640 | | { |
1641 | | MVM_OP_smrt_strify, |
1642 | | "smrt_strify", |
1643 | | " ", |
1644 | | 2, |
1645 | | 1, |
1646 | | 0, |
1647 | | 0, |
1648 | | 0, |
1649 | | 1, |
1650 | | 0, |
1651 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
1652 | | }, |
1653 | | { |
1654 | | MVM_OP_prepargs, |
1655 | | "prepargs", |
1656 | | "+a", |
1657 | | 1, |
1658 | | 0, |
1659 | | 8, |
1660 | | 0, |
1661 | | 0, |
1662 | | 0, |
1663 | | 0, |
1664 | | { MVM_operand_callsite } |
1665 | | }, |
1666 | | { |
1667 | | MVM_OP_arg_i, |
1668 | | "arg_i", |
1669 | | "*a", |
1670 | | 2, |
1671 | | 0, |
1672 | | 0, |
1673 | | 0, |
1674 | | 0, |
1675 | | 0, |
1676 | | 0, |
1677 | | { MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
1678 | | }, |
1679 | | { |
1680 | | MVM_OP_arg_n, |
1681 | | "arg_n", |
1682 | | "*a", |
1683 | | 2, |
1684 | | 0, |
1685 | | 0, |
1686 | | 0, |
1687 | | 0, |
1688 | | 0, |
1689 | | 0, |
1690 | | { MVM_operand_int16, MVM_operand_read_reg | MVM_operand_num64 } |
1691 | | }, |
1692 | | { |
1693 | | MVM_OP_arg_s, |
1694 | | "arg_s", |
1695 | | "*a", |
1696 | | 2, |
1697 | | 0, |
1698 | | 0, |
1699 | | 0, |
1700 | | 0, |
1701 | | 0, |
1702 | | 0, |
1703 | | { MVM_operand_int16, MVM_operand_read_reg | MVM_operand_str } |
1704 | | }, |
1705 | | { |
1706 | | MVM_OP_arg_o, |
1707 | | "arg_o", |
1708 | | "*a", |
1709 | | 2, |
1710 | | 0, |
1711 | | 0, |
1712 | | 0, |
1713 | | 0, |
1714 | | 0, |
1715 | | 0, |
1716 | | { MVM_operand_int16, MVM_operand_read_reg | MVM_operand_obj } |
1717 | | }, |
1718 | | { |
1719 | | MVM_OP_argconst_i, |
1720 | | "argconst_i", |
1721 | | "*a", |
1722 | | 2, |
1723 | | 0, |
1724 | | 0, |
1725 | | 0, |
1726 | | 0, |
1727 | | 0, |
1728 | | 0, |
1729 | | { MVM_operand_int16, MVM_operand_int64 } |
1730 | | }, |
1731 | | { |
1732 | | MVM_OP_argconst_n, |
1733 | | "argconst_n", |
1734 | | "*a", |
1735 | | 2, |
1736 | | 0, |
1737 | | 0, |
1738 | | 0, |
1739 | | 0, |
1740 | | 0, |
1741 | | 0, |
1742 | | { MVM_operand_int16, MVM_operand_num64 } |
1743 | | }, |
1744 | | { |
1745 | | MVM_OP_argconst_s, |
1746 | | "argconst_s", |
1747 | | "*a", |
1748 | | 2, |
1749 | | 0, |
1750 | | 0, |
1751 | | 0, |
1752 | | 0, |
1753 | | 0, |
1754 | | 0, |
1755 | | { MVM_operand_int16, MVM_operand_str } |
1756 | | }, |
1757 | | { |
1758 | | MVM_OP_invoke_v, |
1759 | | "invoke_v", |
1760 | | "-a", |
1761 | | 1, |
1762 | | 0, |
1763 | | 2, |
1764 | | 0, |
1765 | | 0, |
1766 | | 0, |
1767 | | 0, |
1768 | | { MVM_operand_read_reg | MVM_operand_obj } |
1769 | | }, |
1770 | | { |
1771 | | MVM_OP_invoke_i, |
1772 | | "invoke_i", |
1773 | | "-a", |
1774 | | 2, |
1775 | | 0, |
1776 | | 2, |
1777 | | 0, |
1778 | | 0, |
1779 | | 0, |
1780 | | 0, |
1781 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
1782 | | }, |
1783 | | { |
1784 | | MVM_OP_invoke_n, |
1785 | | "invoke_n", |
1786 | | "-a", |
1787 | | 2, |
1788 | | 0, |
1789 | | 2, |
1790 | | 0, |
1791 | | 0, |
1792 | | 0, |
1793 | | 0, |
1794 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
1795 | | }, |
1796 | | { |
1797 | | MVM_OP_invoke_s, |
1798 | | "invoke_s", |
1799 | | "-a", |
1800 | | 2, |
1801 | | 0, |
1802 | | 2, |
1803 | | 0, |
1804 | | 0, |
1805 | | 0, |
1806 | | 0, |
1807 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
1808 | | }, |
1809 | | { |
1810 | | MVM_OP_invoke_o, |
1811 | | "invoke_o", |
1812 | | "-a", |
1813 | | 2, |
1814 | | 0, |
1815 | | 3, |
1816 | | 1, |
1817 | | 0, |
1818 | | 0, |
1819 | | 0, |
1820 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
1821 | | }, |
1822 | | { |
1823 | | MVM_OP_checkarity, |
1824 | | "checkarity", |
1825 | | " ", |
1826 | | 2, |
1827 | | 0, |
1828 | | 0, |
1829 | | 0, |
1830 | | 0, |
1831 | | 0, |
1832 | | 0, |
1833 | | { MVM_operand_int16, MVM_operand_int16 } |
1834 | | }, |
1835 | | { |
1836 | | MVM_OP_param_rp_i, |
1837 | | "param_rp_i", |
1838 | | ".p", |
1839 | | 2, |
1840 | | 1, |
1841 | | 0, |
1842 | | 0, |
1843 | | 1, |
1844 | | 0, |
1845 | | 0, |
1846 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_int16 } |
1847 | | }, |
1848 | | { |
1849 | | MVM_OP_param_rp_n, |
1850 | | "param_rp_n", |
1851 | | ".p", |
1852 | | 2, |
1853 | | 1, |
1854 | | 0, |
1855 | | 0, |
1856 | | 1, |
1857 | | 0, |
1858 | | 0, |
1859 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_int16 } |
1860 | | }, |
1861 | | { |
1862 | | MVM_OP_param_rp_s, |
1863 | | "param_rp_s", |
1864 | | ".p", |
1865 | | 2, |
1866 | | 1, |
1867 | | 0, |
1868 | | 0, |
1869 | | 1, |
1870 | | 0, |
1871 | | 0, |
1872 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_int16 } |
1873 | | }, |
1874 | | { |
1875 | | MVM_OP_param_rp_o, |
1876 | | "param_rp_o", |
1877 | | ".p", |
1878 | | 2, |
1879 | | 1, |
1880 | | 0, |
1881 | | 0, |
1882 | | 1, |
1883 | | 0, |
1884 | | 1, |
1885 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16 } |
1886 | | }, |
1887 | | { |
1888 | | MVM_OP_param_op_i, |
1889 | | "param_op_i", |
1890 | | ".p", |
1891 | | 3, |
1892 | | 1, |
1893 | | 0, |
1894 | | 0, |
1895 | | 1, |
1896 | | 0, |
1897 | | 0, |
1898 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_int16, MVM_operand_ins } |
1899 | | }, |
1900 | | { |
1901 | | MVM_OP_param_op_n, |
1902 | | "param_op_n", |
1903 | | ".p", |
1904 | | 3, |
1905 | | 1, |
1906 | | 0, |
1907 | | 0, |
1908 | | 1, |
1909 | | 0, |
1910 | | 0, |
1911 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_int16, MVM_operand_ins } |
1912 | | }, |
1913 | | { |
1914 | | MVM_OP_param_op_s, |
1915 | | "param_op_s", |
1916 | | ".p", |
1917 | | 3, |
1918 | | 1, |
1919 | | 0, |
1920 | | 0, |
1921 | | 1, |
1922 | | 0, |
1923 | | 0, |
1924 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_int16, MVM_operand_ins } |
1925 | | }, |
1926 | | { |
1927 | | MVM_OP_param_op_o, |
1928 | | "param_op_o", |
1929 | | ".p", |
1930 | | 3, |
1931 | | 1, |
1932 | | 0, |
1933 | | 0, |
1934 | | 1, |
1935 | | 0, |
1936 | | 1, |
1937 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_ins } |
1938 | | }, |
1939 | | { |
1940 | | MVM_OP_param_rn_i, |
1941 | | "param_rn_i", |
1942 | | " ", |
1943 | | 2, |
1944 | | 0, |
1945 | | 0, |
1946 | | 0, |
1947 | | 1, |
1948 | | 0, |
1949 | | 0, |
1950 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_str } |
1951 | | }, |
1952 | | { |
1953 | | MVM_OP_param_rn_n, |
1954 | | "param_rn_n", |
1955 | | " ", |
1956 | | 2, |
1957 | | 0, |
1958 | | 0, |
1959 | | 0, |
1960 | | 1, |
1961 | | 0, |
1962 | | 0, |
1963 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_str } |
1964 | | }, |
1965 | | { |
1966 | | MVM_OP_param_rn_s, |
1967 | | "param_rn_s", |
1968 | | " ", |
1969 | | 2, |
1970 | | 0, |
1971 | | 0, |
1972 | | 0, |
1973 | | 1, |
1974 | | 0, |
1975 | | 0, |
1976 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_str } |
1977 | | }, |
1978 | | { |
1979 | | MVM_OP_param_rn_o, |
1980 | | "param_rn_o", |
1981 | | " ", |
1982 | | 2, |
1983 | | 0, |
1984 | | 0, |
1985 | | 0, |
1986 | | 1, |
1987 | | 0, |
1988 | | 1, |
1989 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
1990 | | }, |
1991 | | { |
1992 | | MVM_OP_param_on_i, |
1993 | | "param_on_i", |
1994 | | " ", |
1995 | | 3, |
1996 | | 0, |
1997 | | 0, |
1998 | | 0, |
1999 | | 1, |
2000 | | 0, |
2001 | | 0, |
2002 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_str, MVM_operand_ins } |
2003 | | }, |
2004 | | { |
2005 | | MVM_OP_param_on_n, |
2006 | | "param_on_n", |
2007 | | " ", |
2008 | | 3, |
2009 | | 0, |
2010 | | 0, |
2011 | | 0, |
2012 | | 1, |
2013 | | 0, |
2014 | | 0, |
2015 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_str, MVM_operand_ins } |
2016 | | }, |
2017 | | { |
2018 | | MVM_OP_param_on_s, |
2019 | | "param_on_s", |
2020 | | " ", |
2021 | | 3, |
2022 | | 0, |
2023 | | 0, |
2024 | | 0, |
2025 | | 1, |
2026 | | 0, |
2027 | | 0, |
2028 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_str, MVM_operand_ins } |
2029 | | }, |
2030 | | { |
2031 | | MVM_OP_param_on_o, |
2032 | | "param_on_o", |
2033 | | " ", |
2034 | | 3, |
2035 | | 0, |
2036 | | 0, |
2037 | | 0, |
2038 | | 1, |
2039 | | 0, |
2040 | | 1, |
2041 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_ins } |
2042 | | }, |
2043 | | { |
2044 | | MVM_OP_param_sp, |
2045 | | "param_sp", |
2046 | | ".p", |
2047 | | 2, |
2048 | | 1, |
2049 | | 0, |
2050 | | 0, |
2051 | | 1, |
2052 | | 0, |
2053 | | 1, |
2054 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16 } |
2055 | | }, |
2056 | | { |
2057 | | MVM_OP_param_sn, |
2058 | | "param_sn", |
2059 | | " ", |
2060 | | 1, |
2061 | | 0, |
2062 | | 0, |
2063 | | 0, |
2064 | | 1, |
2065 | | 0, |
2066 | | 1, |
2067 | | { MVM_operand_write_reg | MVM_operand_obj } |
2068 | | }, |
2069 | | { |
2070 | | MVM_OP_getcode, |
2071 | | "getcode", |
2072 | | " ", |
2073 | | 2, |
2074 | | 1, |
2075 | | 0, |
2076 | | 0, |
2077 | | 0, |
2078 | | 0, |
2079 | | 0, |
2080 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_coderef } |
2081 | | }, |
2082 | | { |
2083 | | MVM_OP_caller, |
2084 | | "caller", |
2085 | | " ", |
2086 | | 2, |
2087 | | 1, |
2088 | | 0, |
2089 | | 0, |
2090 | | 1, |
2091 | | 0, |
2092 | | 0, |
2093 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2094 | | }, |
2095 | | { |
2096 | | MVM_OP_capturelex, |
2097 | | "capturelex", |
2098 | | " ", |
2099 | | 1, |
2100 | | 0, |
2101 | | 0, |
2102 | | 0, |
2103 | | 1, |
2104 | | 0, |
2105 | | 0, |
2106 | | { MVM_operand_read_reg | MVM_operand_obj } |
2107 | | }, |
2108 | | { |
2109 | | MVM_OP_takeclosure, |
2110 | | "takeclosure", |
2111 | | " ", |
2112 | | 2, |
2113 | | 0, |
2114 | | 0, |
2115 | | 0, |
2116 | | 1, |
2117 | | 0, |
2118 | | 0, |
2119 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2120 | | }, |
2121 | | { |
2122 | | MVM_OP_exception, |
2123 | | "exception", |
2124 | | " ", |
2125 | | 1, |
2126 | | 0, |
2127 | | 0, |
2128 | | 0, |
2129 | | 0, |
2130 | | 0, |
2131 | | 0, |
2132 | | { MVM_operand_write_reg | MVM_operand_obj } |
2133 | | }, |
2134 | | { |
2135 | | MVM_OP_bindexmessage, |
2136 | | "bindexmessage", |
2137 | | " ", |
2138 | | 2, |
2139 | | 0, |
2140 | | 0, |
2141 | | 0, |
2142 | | 0, |
2143 | | 0, |
2144 | | 0, |
2145 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
2146 | | }, |
2147 | | { |
2148 | | MVM_OP_bindexpayload, |
2149 | | "bindexpayload", |
2150 | | " ", |
2151 | | 2, |
2152 | | 0, |
2153 | | 0, |
2154 | | 0, |
2155 | | 0, |
2156 | | 0, |
2157 | | 0, |
2158 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2159 | | }, |
2160 | | { |
2161 | | MVM_OP_bindexcategory, |
2162 | | "bindexcategory", |
2163 | | " ", |
2164 | | 2, |
2165 | | 0, |
2166 | | 0, |
2167 | | 0, |
2168 | | 0, |
2169 | | 0, |
2170 | | 0, |
2171 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2172 | | }, |
2173 | | { |
2174 | | MVM_OP_getexmessage, |
2175 | | "getexmessage", |
2176 | | " ", |
2177 | | 2, |
2178 | | 1, |
2179 | | 0, |
2180 | | 0, |
2181 | | 0, |
2182 | | 0, |
2183 | | 0, |
2184 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
2185 | | }, |
2186 | | { |
2187 | | MVM_OP_getexpayload, |
2188 | | "getexpayload", |
2189 | | " ", |
2190 | | 2, |
2191 | | 1, |
2192 | | 0, |
2193 | | 0, |
2194 | | 0, |
2195 | | 0, |
2196 | | 0, |
2197 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2198 | | }, |
2199 | | { |
2200 | | MVM_OP_getexcategory, |
2201 | | "getexcategory", |
2202 | | " ", |
2203 | | 2, |
2204 | | 1, |
2205 | | 0, |
2206 | | 0, |
2207 | | 0, |
2208 | | 0, |
2209 | | 0, |
2210 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
2211 | | }, |
2212 | | { |
2213 | | MVM_OP_throwdyn, |
2214 | | "throwdyn", |
2215 | | " ", |
2216 | | 2, |
2217 | | 0, |
2218 | | 0, |
2219 | | 0, |
2220 | | 0, |
2221 | | 2, |
2222 | | 0, |
2223 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2224 | | }, |
2225 | | { |
2226 | | MVM_OP_throwlex, |
2227 | | "throwlex", |
2228 | | " ", |
2229 | | 2, |
2230 | | 0, |
2231 | | 0, |
2232 | | 0, |
2233 | | 0, |
2234 | | 2, |
2235 | | 0, |
2236 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2237 | | }, |
2238 | | { |
2239 | | MVM_OP_throwlexotic, |
2240 | | "throwlexotic", |
2241 | | " ", |
2242 | | 2, |
2243 | | 0, |
2244 | | 0, |
2245 | | 0, |
2246 | | 0, |
2247 | | 2, |
2248 | | 0, |
2249 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2250 | | }, |
2251 | | { |
2252 | | MVM_OP_throwcatdyn, |
2253 | | "throwcatdyn", |
2254 | | " ", |
2255 | | 2, |
2256 | | 0, |
2257 | | 0, |
2258 | | 0, |
2259 | | 0, |
2260 | | 2, |
2261 | | 0, |
2262 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int64 } |
2263 | | }, |
2264 | | { |
2265 | | MVM_OP_throwcatlex, |
2266 | | "throwcatlex", |
2267 | | " ", |
2268 | | 2, |
2269 | | 0, |
2270 | | 0, |
2271 | | 0, |
2272 | | 0, |
2273 | | 2, |
2274 | | 0, |
2275 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int64 } |
2276 | | }, |
2277 | | { |
2278 | | MVM_OP_throwcatlexotic, |
2279 | | "throwcatlexotic", |
2280 | | " ", |
2281 | | 2, |
2282 | | 0, |
2283 | | 0, |
2284 | | 0, |
2285 | | 0, |
2286 | | 2, |
2287 | | 0, |
2288 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int64 } |
2289 | | }, |
2290 | | { |
2291 | | MVM_OP_die, |
2292 | | "die", |
2293 | | " ", |
2294 | | 2, |
2295 | | 0, |
2296 | | 0, |
2297 | | 0, |
2298 | | 0, |
2299 | | 2, |
2300 | | 0, |
2301 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
2302 | | }, |
2303 | | { |
2304 | | MVM_OP_rethrow, |
2305 | | "rethrow", |
2306 | | " ", |
2307 | | 1, |
2308 | | 0, |
2309 | | 0, |
2310 | | 0, |
2311 | | 0, |
2312 | | 2, |
2313 | | 0, |
2314 | | { MVM_operand_read_reg | MVM_operand_obj } |
2315 | | }, |
2316 | | { |
2317 | | MVM_OP_resume, |
2318 | | "resume", |
2319 | | " ", |
2320 | | 1, |
2321 | | 0, |
2322 | | 0, |
2323 | | 0, |
2324 | | 0, |
2325 | | 2, |
2326 | | 0, |
2327 | | { MVM_operand_read_reg | MVM_operand_obj } |
2328 | | }, |
2329 | | { |
2330 | | MVM_OP_takehandlerresult, |
2331 | | "takehandlerresult", |
2332 | | " ", |
2333 | | 1, |
2334 | | 0, |
2335 | | 0, |
2336 | | 0, |
2337 | | 0, |
2338 | | 0, |
2339 | | 0, |
2340 | | { MVM_operand_write_reg | MVM_operand_obj } |
2341 | | }, |
2342 | | { |
2343 | | MVM_OP_DEPRECATED_33, |
2344 | | "DEPRECATED_33", |
2345 | | " ", |
2346 | | 2, |
2347 | | 0, |
2348 | | 0, |
2349 | | 0, |
2350 | | 0, |
2351 | | 0, |
2352 | | 0, |
2353 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_ins } |
2354 | | }, |
2355 | | { |
2356 | | MVM_OP_DEPRECATED_34, |
2357 | | "DEPRECATED_34", |
2358 | | " ", |
2359 | | 2, |
2360 | | 0, |
2361 | | 0, |
2362 | | 0, |
2363 | | 0, |
2364 | | 0, |
2365 | | 0, |
2366 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2367 | | }, |
2368 | | { |
2369 | | MVM_OP_backtracestrings, |
2370 | | "backtracestrings", |
2371 | | " ", |
2372 | | 2, |
2373 | | 1, |
2374 | | 0, |
2375 | | 0, |
2376 | | 0, |
2377 | | 0, |
2378 | | 0, |
2379 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2380 | | }, |
2381 | | { |
2382 | | MVM_OP_usecapture, |
2383 | | "usecapture", |
2384 | | " ", |
2385 | | 1, |
2386 | | 0, |
2387 | | 0, |
2388 | | 0, |
2389 | | 1, |
2390 | | 0, |
2391 | | 0, |
2392 | | { MVM_operand_write_reg | MVM_operand_obj } |
2393 | | }, |
2394 | | { |
2395 | | MVM_OP_savecapture, |
2396 | | "savecapture", |
2397 | | " ", |
2398 | | 1, |
2399 | | 0, |
2400 | | 0, |
2401 | | 0, |
2402 | | 1, |
2403 | | 0, |
2404 | | 0, |
2405 | | { MVM_operand_write_reg | MVM_operand_obj } |
2406 | | }, |
2407 | | { |
2408 | | MVM_OP_captureposelems, |
2409 | | "captureposelems", |
2410 | | " ", |
2411 | | 2, |
2412 | | 1, |
2413 | | 0, |
2414 | | 0, |
2415 | | 0, |
2416 | | 0, |
2417 | | 0, |
2418 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
2419 | | }, |
2420 | | { |
2421 | | MVM_OP_captureposarg, |
2422 | | "captureposarg", |
2423 | | " ", |
2424 | | 3, |
2425 | | 1, |
2426 | | 0, |
2427 | | 0, |
2428 | | 0, |
2429 | | 0, |
2430 | | 1, |
2431 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2432 | | }, |
2433 | | { |
2434 | | MVM_OP_captureposarg_i, |
2435 | | "captureposarg_i", |
2436 | | " ", |
2437 | | 3, |
2438 | | 1, |
2439 | | 0, |
2440 | | 0, |
2441 | | 0, |
2442 | | 0, |
2443 | | 0, |
2444 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2445 | | }, |
2446 | | { |
2447 | | MVM_OP_captureposarg_n, |
2448 | | "captureposarg_n", |
2449 | | " ", |
2450 | | 3, |
2451 | | 1, |
2452 | | 0, |
2453 | | 0, |
2454 | | 0, |
2455 | | 0, |
2456 | | 0, |
2457 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2458 | | }, |
2459 | | { |
2460 | | MVM_OP_captureposarg_s, |
2461 | | "captureposarg_s", |
2462 | | " ", |
2463 | | 3, |
2464 | | 1, |
2465 | | 0, |
2466 | | 0, |
2467 | | 0, |
2468 | | 0, |
2469 | | 0, |
2470 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2471 | | }, |
2472 | | { |
2473 | | MVM_OP_captureposprimspec, |
2474 | | "captureposprimspec", |
2475 | | " ", |
2476 | | 3, |
2477 | | 1, |
2478 | | 0, |
2479 | | 0, |
2480 | | 0, |
2481 | | 0, |
2482 | | 0, |
2483 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
2484 | | }, |
2485 | | { |
2486 | | MVM_OP_captureexistsnamed, |
2487 | | "captureexistsnamed", |
2488 | | " ", |
2489 | | 3, |
2490 | | 1, |
2491 | | 0, |
2492 | | 0, |
2493 | | 0, |
2494 | | 0, |
2495 | | 0, |
2496 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
2497 | | }, |
2498 | | { |
2499 | | MVM_OP_capturehasnameds, |
2500 | | "capturehasnameds", |
2501 | | " ", |
2502 | | 2, |
2503 | | 1, |
2504 | | 0, |
2505 | | 0, |
2506 | | 0, |
2507 | | 0, |
2508 | | 1, |
2509 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
2510 | | }, |
2511 | | { |
2512 | | MVM_OP_invokewithcapture, |
2513 | | "invokewithcapture", |
2514 | | " ", |
2515 | | 3, |
2516 | | 0, |
2517 | | 0, |
2518 | | 0, |
2519 | | 0, |
2520 | | 1, |
2521 | | 0, |
2522 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2523 | | }, |
2524 | | { |
2525 | | MVM_OP_multicacheadd, |
2526 | | "multicacheadd", |
2527 | | " ", |
2528 | | 4, |
2529 | | 0, |
2530 | | 0, |
2531 | | 0, |
2532 | | 0, |
2533 | | 0, |
2534 | | 0, |
2535 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2536 | | }, |
2537 | | { |
2538 | | MVM_OP_multicachefind, |
2539 | | "multicachefind", |
2540 | | " ", |
2541 | | 3, |
2542 | | 0, |
2543 | | 0, |
2544 | | 0, |
2545 | | 0, |
2546 | | 0, |
2547 | | 0, |
2548 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
2549 | | }, |
2550 | | { |
2551 | | MVM_OP_null_s, |
2552 | | "null_s", |
2553 | | " ", |
2554 | | 1, |
2555 | | 1, |
2556 | | 0, |
2557 | | 0, |
2558 | | 0, |
2559 | | 0, |
2560 | | 0, |
2561 | | { MVM_operand_write_reg | MVM_operand_str } |
2562 | | }, |
2563 | | { |
2564 | | MVM_OP_isnull_s, |
2565 | | "isnull_s", |
2566 | | " ", |
2567 | | 2, |
2568 | | 1, |
2569 | | 0, |
2570 | | 0, |
2571 | | 0, |
2572 | | 0, |
2573 | | 0, |
2574 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2575 | | }, |
2576 | | { |
2577 | | MVM_OP_eq_s, |
2578 | | "eq_s", |
2579 | | " ", |
2580 | | 3, |
2581 | | 1, |
2582 | | 0, |
2583 | | 0, |
2584 | | 0, |
2585 | | 0, |
2586 | | 0, |
2587 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2588 | | }, |
2589 | | { |
2590 | | MVM_OP_ne_s, |
2591 | | "ne_s", |
2592 | | " ", |
2593 | | 3, |
2594 | | 1, |
2595 | | 0, |
2596 | | 0, |
2597 | | 0, |
2598 | | 0, |
2599 | | 0, |
2600 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2601 | | }, |
2602 | | { |
2603 | | MVM_OP_gt_s, |
2604 | | "gt_s", |
2605 | | " ", |
2606 | | 3, |
2607 | | 1, |
2608 | | 0, |
2609 | | 0, |
2610 | | 0, |
2611 | | 0, |
2612 | | 0, |
2613 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2614 | | }, |
2615 | | { |
2616 | | MVM_OP_ge_s, |
2617 | | "ge_s", |
2618 | | " ", |
2619 | | 3, |
2620 | | 1, |
2621 | | 0, |
2622 | | 0, |
2623 | | 0, |
2624 | | 0, |
2625 | | 0, |
2626 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2627 | | }, |
2628 | | { |
2629 | | MVM_OP_lt_s, |
2630 | | "lt_s", |
2631 | | " ", |
2632 | | 3, |
2633 | | 1, |
2634 | | 0, |
2635 | | 0, |
2636 | | 0, |
2637 | | 0, |
2638 | | 0, |
2639 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2640 | | }, |
2641 | | { |
2642 | | MVM_OP_le_s, |
2643 | | "le_s", |
2644 | | " ", |
2645 | | 3, |
2646 | | 1, |
2647 | | 0, |
2648 | | 0, |
2649 | | 0, |
2650 | | 0, |
2651 | | 0, |
2652 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2653 | | }, |
2654 | | { |
2655 | | MVM_OP_cmp_s, |
2656 | | "cmp_s", |
2657 | | " ", |
2658 | | 3, |
2659 | | 1, |
2660 | | 0, |
2661 | | 0, |
2662 | | 0, |
2663 | | 0, |
2664 | | 0, |
2665 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2666 | | }, |
2667 | | { |
2668 | | MVM_OP_eqat_s, |
2669 | | "eqat_s", |
2670 | | " ", |
2671 | | 4, |
2672 | | 1, |
2673 | | 0, |
2674 | | 0, |
2675 | | 0, |
2676 | | 0, |
2677 | | 0, |
2678 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2679 | | }, |
2680 | | { |
2681 | | MVM_OP_eqatic_s, |
2682 | | "eqatic_s", |
2683 | | " ", |
2684 | | 4, |
2685 | | 1, |
2686 | | 0, |
2687 | | 0, |
2688 | | 0, |
2689 | | 0, |
2690 | | 0, |
2691 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2692 | | }, |
2693 | | { |
2694 | | MVM_OP_haveat_s, |
2695 | | "haveat_s", |
2696 | | " ", |
2697 | | 6, |
2698 | | 1, |
2699 | | 0, |
2700 | | 0, |
2701 | | 0, |
2702 | | 0, |
2703 | | 0, |
2704 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2705 | | }, |
2706 | | { |
2707 | | MVM_OP_concat_s, |
2708 | | "concat_s", |
2709 | | " ", |
2710 | | 3, |
2711 | | 1, |
2712 | | 0, |
2713 | | 0, |
2714 | | 0, |
2715 | | 0, |
2716 | | 0, |
2717 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2718 | | }, |
2719 | | { |
2720 | | MVM_OP_repeat_s, |
2721 | | "repeat_s", |
2722 | | " ", |
2723 | | 3, |
2724 | | 1, |
2725 | | 0, |
2726 | | 0, |
2727 | | 0, |
2728 | | 0, |
2729 | | 0, |
2730 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2731 | | }, |
2732 | | { |
2733 | | MVM_OP_substr_s, |
2734 | | "substr_s", |
2735 | | " ", |
2736 | | 4, |
2737 | | 1, |
2738 | | 0, |
2739 | | 0, |
2740 | | 0, |
2741 | | 0, |
2742 | | 0, |
2743 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
2744 | | }, |
2745 | | { |
2746 | | MVM_OP_index_s, |
2747 | | "index_s", |
2748 | | " ", |
2749 | | 4, |
2750 | | 1, |
2751 | | 0, |
2752 | | 0, |
2753 | | 0, |
2754 | | 0, |
2755 | | 0, |
2756 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2757 | | }, |
2758 | | { |
2759 | | MVM_OP_graphs_s, |
2760 | | "graphs_s", |
2761 | | " ", |
2762 | | 2, |
2763 | | 1, |
2764 | | 0, |
2765 | | 0, |
2766 | | 0, |
2767 | | 0, |
2768 | | 0, |
2769 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2770 | | }, |
2771 | | { |
2772 | | MVM_OP_codes_s, |
2773 | | "codes_s", |
2774 | | " ", |
2775 | | 2, |
2776 | | 1, |
2777 | | 0, |
2778 | | 0, |
2779 | | 0, |
2780 | | 0, |
2781 | | 0, |
2782 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2783 | | }, |
2784 | | { |
2785 | | MVM_OP_getcp_s, |
2786 | | "getcp_s", |
2787 | | " ", |
2788 | | 3, |
2789 | | 1, |
2790 | | 0, |
2791 | | 0, |
2792 | | 0, |
2793 | | 0, |
2794 | | 0, |
2795 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2796 | | }, |
2797 | | { |
2798 | | MVM_OP_indexcp_s, |
2799 | | "indexcp_s", |
2800 | | " ", |
2801 | | 3, |
2802 | | 1, |
2803 | | 0, |
2804 | | 0, |
2805 | | 0, |
2806 | | 0, |
2807 | | 0, |
2808 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2809 | | }, |
2810 | | { |
2811 | | MVM_OP_uc, |
2812 | | "uc", |
2813 | | " ", |
2814 | | 2, |
2815 | | 1, |
2816 | | 0, |
2817 | | 0, |
2818 | | 0, |
2819 | | 0, |
2820 | | 0, |
2821 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2822 | | }, |
2823 | | { |
2824 | | MVM_OP_lc, |
2825 | | "lc", |
2826 | | " ", |
2827 | | 2, |
2828 | | 1, |
2829 | | 0, |
2830 | | 0, |
2831 | | 0, |
2832 | | 0, |
2833 | | 0, |
2834 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2835 | | }, |
2836 | | { |
2837 | | MVM_OP_tc, |
2838 | | "tc", |
2839 | | " ", |
2840 | | 2, |
2841 | | 1, |
2842 | | 0, |
2843 | | 0, |
2844 | | 0, |
2845 | | 0, |
2846 | | 0, |
2847 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2848 | | }, |
2849 | | { |
2850 | | MVM_OP_split, |
2851 | | "split", |
2852 | | " ", |
2853 | | 3, |
2854 | | 1, |
2855 | | 0, |
2856 | | 0, |
2857 | | 0, |
2858 | | 0, |
2859 | | 0, |
2860 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
2861 | | }, |
2862 | | { |
2863 | | MVM_OP_join, |
2864 | | "join", |
2865 | | " ", |
2866 | | 3, |
2867 | | 1, |
2868 | | 0, |
2869 | | 0, |
2870 | | 0, |
2871 | | 0, |
2872 | | 0, |
2873 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
2874 | | }, |
2875 | | { |
2876 | | MVM_OP_getcpbyname, |
2877 | | "getcpbyname", |
2878 | | " ", |
2879 | | 2, |
2880 | | 1, |
2881 | | 0, |
2882 | | 0, |
2883 | | 0, |
2884 | | 0, |
2885 | | 0, |
2886 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2887 | | }, |
2888 | | { |
2889 | | MVM_OP_indexat, |
2890 | | "indexat", |
2891 | | " ", |
2892 | | 4, |
2893 | | 0, |
2894 | | 0, |
2895 | | 0, |
2896 | | 0, |
2897 | | 0, |
2898 | | 0, |
2899 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_str, MVM_operand_ins } |
2900 | | }, |
2901 | | { |
2902 | | MVM_OP_indexnat, |
2903 | | "indexnat", |
2904 | | " ", |
2905 | | 4, |
2906 | | 0, |
2907 | | 0, |
2908 | | 0, |
2909 | | 0, |
2910 | | 0, |
2911 | | 0, |
2912 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_str, MVM_operand_ins } |
2913 | | }, |
2914 | | { |
2915 | | MVM_OP_unipropcode, |
2916 | | "unipropcode", |
2917 | | " ", |
2918 | | 2, |
2919 | | 1, |
2920 | | 0, |
2921 | | 0, |
2922 | | 0, |
2923 | | 0, |
2924 | | 0, |
2925 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2926 | | }, |
2927 | | { |
2928 | | MVM_OP_unipvalcode, |
2929 | | "unipvalcode", |
2930 | | " ", |
2931 | | 3, |
2932 | | 1, |
2933 | | 0, |
2934 | | 0, |
2935 | | 0, |
2936 | | 0, |
2937 | | 0, |
2938 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2939 | | }, |
2940 | | { |
2941 | | MVM_OP_hasuniprop, |
2942 | | "hasuniprop", |
2943 | | " ", |
2944 | | 5, |
2945 | | 1, |
2946 | | 0, |
2947 | | 0, |
2948 | | 0, |
2949 | | 0, |
2950 | | 0, |
2951 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
2952 | | }, |
2953 | | { |
2954 | | MVM_OP_hasunipropc, |
2955 | | "hasunipropc", |
2956 | | " ", |
2957 | | 5, |
2958 | | 1, |
2959 | | 0, |
2960 | | 0, |
2961 | | 0, |
2962 | | 0, |
2963 | | 0, |
2964 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_int16, MVM_operand_int16 } |
2965 | | }, |
2966 | | { |
2967 | | MVM_OP_chars, |
2968 | | "chars", |
2969 | | " ", |
2970 | | 2, |
2971 | | 1, |
2972 | | 0, |
2973 | | 0, |
2974 | | 0, |
2975 | | 0, |
2976 | | 0, |
2977 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
2978 | | }, |
2979 | | { |
2980 | | MVM_OP_chr, |
2981 | | "chr", |
2982 | | " ", |
2983 | | 2, |
2984 | | 1, |
2985 | | 0, |
2986 | | 0, |
2987 | | 0, |
2988 | | 0, |
2989 | | 0, |
2990 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
2991 | | }, |
2992 | | { |
2993 | | MVM_OP_ordfirst, |
2994 | | "ordfirst", |
2995 | | " ", |
2996 | | 2, |
2997 | | 1, |
2998 | | 0, |
2999 | | 0, |
3000 | | 0, |
3001 | | 0, |
3002 | | 0, |
3003 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
3004 | | }, |
3005 | | { |
3006 | | MVM_OP_ordat, |
3007 | | "ordat", |
3008 | | " ", |
3009 | | 3, |
3010 | | 1, |
3011 | | 0, |
3012 | | 0, |
3013 | | 0, |
3014 | | 0, |
3015 | | 0, |
3016 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
3017 | | }, |
3018 | | { |
3019 | | MVM_OP_rindexfrom, |
3020 | | "rindexfrom", |
3021 | | " ", |
3022 | | 4, |
3023 | | 1, |
3024 | | 0, |
3025 | | 0, |
3026 | | 0, |
3027 | | 0, |
3028 | | 0, |
3029 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
3030 | | }, |
3031 | | { |
3032 | | MVM_OP_escape, |
3033 | | "escape", |
3034 | | " ", |
3035 | | 2, |
3036 | | 1, |
3037 | | 0, |
3038 | | 0, |
3039 | | 0, |
3040 | | 0, |
3041 | | 0, |
3042 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
3043 | | }, |
3044 | | { |
3045 | | MVM_OP_flip, |
3046 | | "flip", |
3047 | | " ", |
3048 | | 2, |
3049 | | 1, |
3050 | | 0, |
3051 | | 0, |
3052 | | 0, |
3053 | | 0, |
3054 | | 0, |
3055 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
3056 | | }, |
3057 | | { |
3058 | | MVM_OP_setbuffersize_fh, |
3059 | | "setbuffersize_fh", |
3060 | | " ", |
3061 | | 2, |
3062 | | 0, |
3063 | | 0, |
3064 | | 0, |
3065 | | 0, |
3066 | | 0, |
3067 | | 0, |
3068 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
3069 | | }, |
3070 | | { |
3071 | | MVM_OP_iscclass, |
3072 | | "iscclass", |
3073 | | " ", |
3074 | | 4, |
3075 | | 1, |
3076 | | 0, |
3077 | | 0, |
3078 | | 0, |
3079 | | 0, |
3080 | | 0, |
3081 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
3082 | | }, |
3083 | | { |
3084 | | MVM_OP_findcclass, |
3085 | | "findcclass", |
3086 | | " ", |
3087 | | 5, |
3088 | | 1, |
3089 | | 0, |
3090 | | 0, |
3091 | | 0, |
3092 | | 0, |
3093 | | 0, |
3094 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
3095 | | }, |
3096 | | { |
3097 | | MVM_OP_findnotcclass, |
3098 | | "findnotcclass", |
3099 | | " ", |
3100 | | 5, |
3101 | | 1, |
3102 | | 0, |
3103 | | 0, |
3104 | | 0, |
3105 | | 0, |
3106 | | 0, |
3107 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
3108 | | }, |
3109 | | { |
3110 | | MVM_OP_nfafromstatelist, |
3111 | | "nfafromstatelist", |
3112 | | " ", |
3113 | | 3, |
3114 | | 0, |
3115 | | 0, |
3116 | | 0, |
3117 | | 0, |
3118 | | 0, |
3119 | | 0, |
3120 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3121 | | }, |
3122 | | { |
3123 | | MVM_OP_nfarunproto, |
3124 | | "nfarunproto", |
3125 | | " ", |
3126 | | 4, |
3127 | | 0, |
3128 | | 0, |
3129 | | 0, |
3130 | | 0, |
3131 | | 0, |
3132 | | 0, |
3133 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
3134 | | }, |
3135 | | { |
3136 | | MVM_OP_nfarunalt, |
3137 | | "nfarunalt", |
3138 | | " ", |
3139 | | 6, |
3140 | | 0, |
3141 | | 0, |
3142 | | 0, |
3143 | | 0, |
3144 | | 0, |
3145 | | 0, |
3146 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3147 | | }, |
3148 | | { |
3149 | | MVM_OP_radix, |
3150 | | "radix", |
3151 | | " ", |
3152 | | 5, |
3153 | | 0, |
3154 | | 0, |
3155 | | 0, |
3156 | | 0, |
3157 | | 0, |
3158 | | 1, |
3159 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
3160 | | }, |
3161 | | { |
3162 | | MVM_OP_encode, |
3163 | | "encode", |
3164 | | " ", |
3165 | | 4, |
3166 | | 0, |
3167 | | 0, |
3168 | | 0, |
3169 | | 0, |
3170 | | 0, |
3171 | | 0, |
3172 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
3173 | | }, |
3174 | | { |
3175 | | MVM_OP_decode, |
3176 | | "decode", |
3177 | | " ", |
3178 | | 3, |
3179 | | 0, |
3180 | | 0, |
3181 | | 0, |
3182 | | 0, |
3183 | | 0, |
3184 | | 0, |
3185 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3186 | | }, |
3187 | | { |
3188 | | MVM_OP_istrue_s, |
3189 | | "istrue_s", |
3190 | | " ", |
3191 | | 2, |
3192 | | 1, |
3193 | | 0, |
3194 | | 0, |
3195 | | 0, |
3196 | | 0, |
3197 | | 0, |
3198 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
3199 | | }, |
3200 | | { |
3201 | | MVM_OP_isfalse_s, |
3202 | | "isfalse_s", |
3203 | | " ", |
3204 | | 2, |
3205 | | 1, |
3206 | | 0, |
3207 | | 0, |
3208 | | 0, |
3209 | | 0, |
3210 | | 0, |
3211 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
3212 | | }, |
3213 | | { |
3214 | | MVM_OP_null, |
3215 | | "null", |
3216 | | " ", |
3217 | | 1, |
3218 | | 1, |
3219 | | 0, |
3220 | | 0, |
3221 | | 0, |
3222 | | 0, |
3223 | | 0, |
3224 | | { MVM_operand_write_reg | MVM_operand_obj } |
3225 | | }, |
3226 | | { |
3227 | | MVM_OP_isnull, |
3228 | | "isnull", |
3229 | | " ", |
3230 | | 2, |
3231 | | 1, |
3232 | | 0, |
3233 | | 0, |
3234 | | 0, |
3235 | | 0, |
3236 | | 0, |
3237 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3238 | | }, |
3239 | | { |
3240 | | MVM_OP_ifnonnull, |
3241 | | "ifnonnull", |
3242 | | " ", |
3243 | | 2, |
3244 | | 0, |
3245 | | 0, |
3246 | | 0, |
3247 | | 0, |
3248 | | 0, |
3249 | | 0, |
3250 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_ins } |
3251 | | }, |
3252 | | { |
3253 | | MVM_OP_findmeth, |
3254 | | "findmeth", |
3255 | | " ", |
3256 | | 3, |
3257 | | 1, |
3258 | | 0, |
3259 | | 0, |
3260 | | 0, |
3261 | | 1, |
3262 | | 0, |
3263 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str } |
3264 | | }, |
3265 | | { |
3266 | | MVM_OP_findmeth_s, |
3267 | | "findmeth_s", |
3268 | | " ", |
3269 | | 3, |
3270 | | 1, |
3271 | | 0, |
3272 | | 0, |
3273 | | 0, |
3274 | | 1, |
3275 | | 0, |
3276 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3277 | | }, |
3278 | | { |
3279 | | MVM_OP_can, |
3280 | | "can", |
3281 | | " ", |
3282 | | 3, |
3283 | | 1, |
3284 | | 0, |
3285 | | 0, |
3286 | | 0, |
3287 | | 1, |
3288 | | 0, |
3289 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str } |
3290 | | }, |
3291 | | { |
3292 | | MVM_OP_can_s, |
3293 | | "can_s", |
3294 | | " ", |
3295 | | 3, |
3296 | | 1, |
3297 | | 0, |
3298 | | 0, |
3299 | | 0, |
3300 | | 1, |
3301 | | 0, |
3302 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3303 | | }, |
3304 | | { |
3305 | | MVM_OP_create, |
3306 | | "create", |
3307 | | " ", |
3308 | | 2, |
3309 | | 1, |
3310 | | 0, |
3311 | | 0, |
3312 | | 0, |
3313 | | 0, |
3314 | | 0, |
3315 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3316 | | }, |
3317 | | { |
3318 | | MVM_OP_clone, |
3319 | | "clone", |
3320 | | " ", |
3321 | | 2, |
3322 | | 1, |
3323 | | 0, |
3324 | | 0, |
3325 | | 0, |
3326 | | 0, |
3327 | | 0, |
3328 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3329 | | }, |
3330 | | { |
3331 | | MVM_OP_isconcrete, |
3332 | | "isconcrete", |
3333 | | " ", |
3334 | | 2, |
3335 | | 1, |
3336 | | 0, |
3337 | | 0, |
3338 | | 0, |
3339 | | 0, |
3340 | | 0, |
3341 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3342 | | }, |
3343 | | { |
3344 | | MVM_OP_rebless, |
3345 | | "rebless", |
3346 | | " ", |
3347 | | 3, |
3348 | | 0, |
3349 | | 1, |
3350 | | 0, |
3351 | | 0, |
3352 | | 0, |
3353 | | 0, |
3354 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3355 | | }, |
3356 | | { |
3357 | | MVM_OP_istype, |
3358 | | "istype", |
3359 | | " ", |
3360 | | 3, |
3361 | | 1, |
3362 | | 0, |
3363 | | 0, |
3364 | | 0, |
3365 | | 1, |
3366 | | 0, |
3367 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3368 | | }, |
3369 | | { |
3370 | | MVM_OP_objprimspec, |
3371 | | "objprimspec", |
3372 | | " ", |
3373 | | 2, |
3374 | | 1, |
3375 | | 0, |
3376 | | 0, |
3377 | | 0, |
3378 | | 0, |
3379 | | 0, |
3380 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3381 | | }, |
3382 | | { |
3383 | | MVM_OP_gethow, |
3384 | | "gethow", |
3385 | | " ", |
3386 | | 2, |
3387 | | 1, |
3388 | | 0, |
3389 | | 0, |
3390 | | 0, |
3391 | | 0, |
3392 | | 0, |
3393 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3394 | | }, |
3395 | | { |
3396 | | MVM_OP_getwhat, |
3397 | | "getwhat", |
3398 | | " ", |
3399 | | 2, |
3400 | | 1, |
3401 | | 0, |
3402 | | 0, |
3403 | | 0, |
3404 | | 0, |
3405 | | 0, |
3406 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3407 | | }, |
3408 | | { |
3409 | | MVM_OP_getwho, |
3410 | | "getwho", |
3411 | | " ", |
3412 | | 2, |
3413 | | 1, |
3414 | | 0, |
3415 | | 0, |
3416 | | 0, |
3417 | | 0, |
3418 | | 0, |
3419 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3420 | | }, |
3421 | | { |
3422 | | MVM_OP_setwho, |
3423 | | "setwho", |
3424 | | " ", |
3425 | | 3, |
3426 | | 0, |
3427 | | 0, |
3428 | | 0, |
3429 | | 0, |
3430 | | 0, |
3431 | | 0, |
3432 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3433 | | }, |
3434 | | { |
3435 | | MVM_OP_reprname, |
3436 | | "reprname", |
3437 | | " ", |
3438 | | 2, |
3439 | | 1, |
3440 | | 0, |
3441 | | 0, |
3442 | | 0, |
3443 | | 0, |
3444 | | 0, |
3445 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
3446 | | }, |
3447 | | { |
3448 | | MVM_OP_getwhere, |
3449 | | "getwhere", |
3450 | | " ", |
3451 | | 2, |
3452 | | 1, |
3453 | | 0, |
3454 | | 0, |
3455 | | 0, |
3456 | | 0, |
3457 | | 0, |
3458 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3459 | | }, |
3460 | | { |
3461 | | MVM_OP_eqaddr, |
3462 | | "eqaddr", |
3463 | | " ", |
3464 | | 3, |
3465 | | 1, |
3466 | | 0, |
3467 | | 0, |
3468 | | 0, |
3469 | | 0, |
3470 | | 0, |
3471 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3472 | | }, |
3473 | | { |
3474 | | MVM_OP_bindattr_i, |
3475 | | "bindattr_i", |
3476 | | " ", |
3477 | | 5, |
3478 | | 0, |
3479 | | 0, |
3480 | | 0, |
3481 | | 0, |
3482 | | 0, |
3483 | | 0, |
3484 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_int16 } |
3485 | | }, |
3486 | | { |
3487 | | MVM_OP_bindattr_n, |
3488 | | "bindattr_n", |
3489 | | " ", |
3490 | | 5, |
3491 | | 0, |
3492 | | 0, |
3493 | | 0, |
3494 | | 0, |
3495 | | 0, |
3496 | | 0, |
3497 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_int16 } |
3498 | | }, |
3499 | | { |
3500 | | MVM_OP_bindattr_s, |
3501 | | "bindattr_s", |
3502 | | " ", |
3503 | | 5, |
3504 | | 0, |
3505 | | 0, |
3506 | | 0, |
3507 | | 0, |
3508 | | 0, |
3509 | | 0, |
3510 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_int16 } |
3511 | | }, |
3512 | | { |
3513 | | MVM_OP_bindattr_o, |
3514 | | "bindattr_o", |
3515 | | " ", |
3516 | | 5, |
3517 | | 0, |
3518 | | 0, |
3519 | | 0, |
3520 | | 0, |
3521 | | 0, |
3522 | | 0, |
3523 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
3524 | | }, |
3525 | | { |
3526 | | MVM_OP_bindattrs_i, |
3527 | | "bindattrs_i", |
3528 | | " ", |
3529 | | 4, |
3530 | | 0, |
3531 | | 0, |
3532 | | 0, |
3533 | | 0, |
3534 | | 0, |
3535 | | 0, |
3536 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
3537 | | }, |
3538 | | { |
3539 | | MVM_OP_bindattrs_n, |
3540 | | "bindattrs_n", |
3541 | | " ", |
3542 | | 4, |
3543 | | 0, |
3544 | | 0, |
3545 | | 0, |
3546 | | 0, |
3547 | | 0, |
3548 | | 0, |
3549 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_num64 } |
3550 | | }, |
3551 | | { |
3552 | | MVM_OP_bindattrs_s, |
3553 | | "bindattrs_s", |
3554 | | " ", |
3555 | | 4, |
3556 | | 0, |
3557 | | 0, |
3558 | | 0, |
3559 | | 0, |
3560 | | 0, |
3561 | | 0, |
3562 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
3563 | | }, |
3564 | | { |
3565 | | MVM_OP_bindattrs_o, |
3566 | | "bindattrs_o", |
3567 | | " ", |
3568 | | 4, |
3569 | | 0, |
3570 | | 0, |
3571 | | 0, |
3572 | | 0, |
3573 | | 0, |
3574 | | 0, |
3575 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
3576 | | }, |
3577 | | { |
3578 | | MVM_OP_getattr_i, |
3579 | | "getattr_i", |
3580 | | " ", |
3581 | | 5, |
3582 | | 0, |
3583 | | 0, |
3584 | | 0, |
3585 | | 0, |
3586 | | 0, |
3587 | | 0, |
3588 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
3589 | | }, |
3590 | | { |
3591 | | MVM_OP_getattr_n, |
3592 | | "getattr_n", |
3593 | | " ", |
3594 | | 5, |
3595 | | 0, |
3596 | | 0, |
3597 | | 0, |
3598 | | 0, |
3599 | | 0, |
3600 | | 0, |
3601 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
3602 | | }, |
3603 | | { |
3604 | | MVM_OP_getattr_s, |
3605 | | "getattr_s", |
3606 | | " ", |
3607 | | 5, |
3608 | | 0, |
3609 | | 0, |
3610 | | 0, |
3611 | | 0, |
3612 | | 0, |
3613 | | 0, |
3614 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
3615 | | }, |
3616 | | { |
3617 | | MVM_OP_getattr_o, |
3618 | | "getattr_o", |
3619 | | " ", |
3620 | | 5, |
3621 | | 0, |
3622 | | 1, |
3623 | | 1, |
3624 | | 0, |
3625 | | 0, |
3626 | | 0, |
3627 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
3628 | | }, |
3629 | | { |
3630 | | MVM_OP_getattrs_i, |
3631 | | "getattrs_i", |
3632 | | " ", |
3633 | | 4, |
3634 | | 0, |
3635 | | 0, |
3636 | | 0, |
3637 | | 0, |
3638 | | 0, |
3639 | | 0, |
3640 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3641 | | }, |
3642 | | { |
3643 | | MVM_OP_getattrs_n, |
3644 | | "getattrs_n", |
3645 | | " ", |
3646 | | 4, |
3647 | | 0, |
3648 | | 0, |
3649 | | 0, |
3650 | | 0, |
3651 | | 0, |
3652 | | 0, |
3653 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3654 | | }, |
3655 | | { |
3656 | | MVM_OP_getattrs_s, |
3657 | | "getattrs_s", |
3658 | | " ", |
3659 | | 4, |
3660 | | 0, |
3661 | | 0, |
3662 | | 0, |
3663 | | 0, |
3664 | | 0, |
3665 | | 0, |
3666 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3667 | | }, |
3668 | | { |
3669 | | MVM_OP_getattrs_o, |
3670 | | "getattrs_o", |
3671 | | " ", |
3672 | | 4, |
3673 | | 0, |
3674 | | 1, |
3675 | | 1, |
3676 | | 0, |
3677 | | 0, |
3678 | | 0, |
3679 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3680 | | }, |
3681 | | { |
3682 | | MVM_OP_attrinited, |
3683 | | "attrinited", |
3684 | | " ", |
3685 | | 4, |
3686 | | 0, |
3687 | | 0, |
3688 | | 0, |
3689 | | 0, |
3690 | | 0, |
3691 | | 0, |
3692 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3693 | | }, |
3694 | | { |
3695 | | MVM_OP_box_i, |
3696 | | "box_i", |
3697 | | " ", |
3698 | | 3, |
3699 | | 1, |
3700 | | 0, |
3701 | | 0, |
3702 | | 0, |
3703 | | 0, |
3704 | | 0, |
3705 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3706 | | }, |
3707 | | { |
3708 | | MVM_OP_box_n, |
3709 | | "box_n", |
3710 | | " ", |
3711 | | 3, |
3712 | | 1, |
3713 | | 0, |
3714 | | 0, |
3715 | | 0, |
3716 | | 0, |
3717 | | 0, |
3718 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
3719 | | }, |
3720 | | { |
3721 | | MVM_OP_box_s, |
3722 | | "box_s", |
3723 | | " ", |
3724 | | 3, |
3725 | | 1, |
3726 | | 0, |
3727 | | 0, |
3728 | | 0, |
3729 | | 0, |
3730 | | 0, |
3731 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
3732 | | }, |
3733 | | { |
3734 | | MVM_OP_unbox_i, |
3735 | | "unbox_i", |
3736 | | " ", |
3737 | | 2, |
3738 | | 1, |
3739 | | 0, |
3740 | | 0, |
3741 | | 0, |
3742 | | 0, |
3743 | | 0, |
3744 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3745 | | }, |
3746 | | { |
3747 | | MVM_OP_unbox_n, |
3748 | | "unbox_n", |
3749 | | " ", |
3750 | | 2, |
3751 | | 1, |
3752 | | 0, |
3753 | | 0, |
3754 | | 0, |
3755 | | 0, |
3756 | | 0, |
3757 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
3758 | | }, |
3759 | | { |
3760 | | MVM_OP_unbox_s, |
3761 | | "unbox_s", |
3762 | | " ", |
3763 | | 2, |
3764 | | 1, |
3765 | | 0, |
3766 | | 0, |
3767 | | 0, |
3768 | | 0, |
3769 | | 0, |
3770 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
3771 | | }, |
3772 | | { |
3773 | | MVM_OP_atpos_i, |
3774 | | "atpos_i", |
3775 | | " ", |
3776 | | 3, |
3777 | | 0, |
3778 | | 0, |
3779 | | 0, |
3780 | | 0, |
3781 | | 0, |
3782 | | 0, |
3783 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
3784 | | }, |
3785 | | { |
3786 | | MVM_OP_atpos_n, |
3787 | | "atpos_n", |
3788 | | " ", |
3789 | | 3, |
3790 | | 0, |
3791 | | 0, |
3792 | | 0, |
3793 | | 0, |
3794 | | 0, |
3795 | | 0, |
3796 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
3797 | | }, |
3798 | | { |
3799 | | MVM_OP_atpos_s, |
3800 | | "atpos_s", |
3801 | | " ", |
3802 | | 3, |
3803 | | 0, |
3804 | | 0, |
3805 | | 0, |
3806 | | 0, |
3807 | | 0, |
3808 | | 0, |
3809 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
3810 | | }, |
3811 | | { |
3812 | | MVM_OP_atpos_o, |
3813 | | "atpos_o", |
3814 | | " ", |
3815 | | 3, |
3816 | | 0, |
3817 | | 0, |
3818 | | 0, |
3819 | | 0, |
3820 | | 0, |
3821 | | 0, |
3822 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
3823 | | }, |
3824 | | { |
3825 | | MVM_OP_bindpos_i, |
3826 | | "bindpos_i", |
3827 | | " ", |
3828 | | 3, |
3829 | | 0, |
3830 | | 0, |
3831 | | 0, |
3832 | | 0, |
3833 | | 0, |
3834 | | 0, |
3835 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
3836 | | }, |
3837 | | { |
3838 | | MVM_OP_bindpos_n, |
3839 | | "bindpos_n", |
3840 | | " ", |
3841 | | 3, |
3842 | | 0, |
3843 | | 0, |
3844 | | 0, |
3845 | | 0, |
3846 | | 0, |
3847 | | 0, |
3848 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64 } |
3849 | | }, |
3850 | | { |
3851 | | MVM_OP_bindpos_s, |
3852 | | "bindpos_s", |
3853 | | " ", |
3854 | | 3, |
3855 | | 0, |
3856 | | 0, |
3857 | | 0, |
3858 | | 0, |
3859 | | 0, |
3860 | | 0, |
3861 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
3862 | | }, |
3863 | | { |
3864 | | MVM_OP_bindpos_o, |
3865 | | "bindpos_o", |
3866 | | " ", |
3867 | | 3, |
3868 | | 0, |
3869 | | 0, |
3870 | | 0, |
3871 | | 0, |
3872 | | 0, |
3873 | | 0, |
3874 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3875 | | }, |
3876 | | { |
3877 | | MVM_OP_push_i, |
3878 | | "push_i", |
3879 | | " ", |
3880 | | 2, |
3881 | | 0, |
3882 | | 0, |
3883 | | 0, |
3884 | | 0, |
3885 | | 0, |
3886 | | 0, |
3887 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
3888 | | }, |
3889 | | { |
3890 | | MVM_OP_push_n, |
3891 | | "push_n", |
3892 | | " ", |
3893 | | 2, |
3894 | | 0, |
3895 | | 0, |
3896 | | 0, |
3897 | | 0, |
3898 | | 0, |
3899 | | 0, |
3900 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64 } |
3901 | | }, |
3902 | | { |
3903 | | MVM_OP_push_s, |
3904 | | "push_s", |
3905 | | " ", |
3906 | | 2, |
3907 | | 0, |
3908 | | 0, |
3909 | | 0, |
3910 | | 0, |
3911 | | 0, |
3912 | | 0, |
3913 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
3914 | | }, |
3915 | | { |
3916 | | MVM_OP_push_o, |
3917 | | "push_o", |
3918 | | " ", |
3919 | | 2, |
3920 | | 0, |
3921 | | 0, |
3922 | | 0, |
3923 | | 0, |
3924 | | 0, |
3925 | | 0, |
3926 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3927 | | }, |
3928 | | { |
3929 | | MVM_OP_pop_i, |
3930 | | "pop_i", |
3931 | | " ", |
3932 | | 2, |
3933 | | 0, |
3934 | | 0, |
3935 | | 0, |
3936 | | 0, |
3937 | | 0, |
3938 | | 0, |
3939 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3940 | | }, |
3941 | | { |
3942 | | MVM_OP_pop_n, |
3943 | | "pop_n", |
3944 | | " ", |
3945 | | 2, |
3946 | | 0, |
3947 | | 0, |
3948 | | 0, |
3949 | | 0, |
3950 | | 0, |
3951 | | 0, |
3952 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
3953 | | }, |
3954 | | { |
3955 | | MVM_OP_pop_s, |
3956 | | "pop_s", |
3957 | | " ", |
3958 | | 2, |
3959 | | 0, |
3960 | | 0, |
3961 | | 0, |
3962 | | 0, |
3963 | | 0, |
3964 | | 0, |
3965 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
3966 | | }, |
3967 | | { |
3968 | | MVM_OP_pop_o, |
3969 | | "pop_o", |
3970 | | " ", |
3971 | | 2, |
3972 | | 0, |
3973 | | 0, |
3974 | | 0, |
3975 | | 0, |
3976 | | 0, |
3977 | | 0, |
3978 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
3979 | | }, |
3980 | | { |
3981 | | MVM_OP_shift_i, |
3982 | | "shift_i", |
3983 | | " ", |
3984 | | 2, |
3985 | | 0, |
3986 | | 0, |
3987 | | 0, |
3988 | | 0, |
3989 | | 0, |
3990 | | 0, |
3991 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
3992 | | }, |
3993 | | { |
3994 | | MVM_OP_shift_n, |
3995 | | "shift_n", |
3996 | | " ", |
3997 | | 2, |
3998 | | 0, |
3999 | | 0, |
4000 | | 0, |
4001 | | 0, |
4002 | | 0, |
4003 | | 0, |
4004 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
4005 | | }, |
4006 | | { |
4007 | | MVM_OP_shift_s, |
4008 | | "shift_s", |
4009 | | " ", |
4010 | | 2, |
4011 | | 0, |
4012 | | 0, |
4013 | | 0, |
4014 | | 0, |
4015 | | 0, |
4016 | | 0, |
4017 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4018 | | }, |
4019 | | { |
4020 | | MVM_OP_shift_o, |
4021 | | "shift_o", |
4022 | | " ", |
4023 | | 2, |
4024 | | 0, |
4025 | | 0, |
4026 | | 0, |
4027 | | 0, |
4028 | | 0, |
4029 | | 0, |
4030 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4031 | | }, |
4032 | | { |
4033 | | MVM_OP_unshift_i, |
4034 | | "unshift_i", |
4035 | | " ", |
4036 | | 2, |
4037 | | 0, |
4038 | | 0, |
4039 | | 0, |
4040 | | 0, |
4041 | | 0, |
4042 | | 0, |
4043 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
4044 | | }, |
4045 | | { |
4046 | | MVM_OP_unshift_n, |
4047 | | "unshift_n", |
4048 | | " ", |
4049 | | 2, |
4050 | | 0, |
4051 | | 0, |
4052 | | 0, |
4053 | | 0, |
4054 | | 0, |
4055 | | 0, |
4056 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64 } |
4057 | | }, |
4058 | | { |
4059 | | MVM_OP_unshift_s, |
4060 | | "unshift_s", |
4061 | | " ", |
4062 | | 2, |
4063 | | 0, |
4064 | | 0, |
4065 | | 0, |
4066 | | 0, |
4067 | | 0, |
4068 | | 0, |
4069 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4070 | | }, |
4071 | | { |
4072 | | MVM_OP_unshift_o, |
4073 | | "unshift_o", |
4074 | | " ", |
4075 | | 2, |
4076 | | 0, |
4077 | | 0, |
4078 | | 0, |
4079 | | 0, |
4080 | | 0, |
4081 | | 0, |
4082 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4083 | | }, |
4084 | | { |
4085 | | MVM_OP_splice, |
4086 | | "splice", |
4087 | | " ", |
4088 | | 4, |
4089 | | 0, |
4090 | | 0, |
4091 | | 0, |
4092 | | 0, |
4093 | | 0, |
4094 | | 0, |
4095 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
4096 | | }, |
4097 | | { |
4098 | | MVM_OP_setelemspos, |
4099 | | "setelemspos", |
4100 | | " ", |
4101 | | 2, |
4102 | | 0, |
4103 | | 0, |
4104 | | 0, |
4105 | | 0, |
4106 | | 0, |
4107 | | 0, |
4108 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
4109 | | }, |
4110 | | { |
4111 | | MVM_OP_existspos, |
4112 | | "existspos", |
4113 | | " ", |
4114 | | 3, |
4115 | | 1, |
4116 | | 0, |
4117 | | 0, |
4118 | | 0, |
4119 | | 0, |
4120 | | 0, |
4121 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
4122 | | }, |
4123 | | { |
4124 | | MVM_OP_atkey_i, |
4125 | | "atkey_i", |
4126 | | " ", |
4127 | | 3, |
4128 | | 0, |
4129 | | 0, |
4130 | | 0, |
4131 | | 0, |
4132 | | 0, |
4133 | | 0, |
4134 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4135 | | }, |
4136 | | { |
4137 | | MVM_OP_atkey_n, |
4138 | | "atkey_n", |
4139 | | " ", |
4140 | | 3, |
4141 | | 0, |
4142 | | 0, |
4143 | | 0, |
4144 | | 0, |
4145 | | 0, |
4146 | | 0, |
4147 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4148 | | }, |
4149 | | { |
4150 | | MVM_OP_atkey_s, |
4151 | | "atkey_s", |
4152 | | " ", |
4153 | | 3, |
4154 | | 0, |
4155 | | 0, |
4156 | | 0, |
4157 | | 0, |
4158 | | 0, |
4159 | | 0, |
4160 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4161 | | }, |
4162 | | { |
4163 | | MVM_OP_atkey_o, |
4164 | | "atkey_o", |
4165 | | " ", |
4166 | | 3, |
4167 | | 0, |
4168 | | 0, |
4169 | | 0, |
4170 | | 0, |
4171 | | 0, |
4172 | | 0, |
4173 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4174 | | }, |
4175 | | { |
4176 | | MVM_OP_bindkey_i, |
4177 | | "bindkey_i", |
4178 | | " ", |
4179 | | 3, |
4180 | | 0, |
4181 | | 0, |
4182 | | 0, |
4183 | | 0, |
4184 | | 0, |
4185 | | 0, |
4186 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
4187 | | }, |
4188 | | { |
4189 | | MVM_OP_bindkey_n, |
4190 | | "bindkey_n", |
4191 | | " ", |
4192 | | 3, |
4193 | | 0, |
4194 | | 0, |
4195 | | 0, |
4196 | | 0, |
4197 | | 0, |
4198 | | 0, |
4199 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_num64 } |
4200 | | }, |
4201 | | { |
4202 | | MVM_OP_bindkey_s, |
4203 | | "bindkey_s", |
4204 | | " ", |
4205 | | 3, |
4206 | | 0, |
4207 | | 0, |
4208 | | 0, |
4209 | | 0, |
4210 | | 0, |
4211 | | 0, |
4212 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
4213 | | }, |
4214 | | { |
4215 | | MVM_OP_bindkey_o, |
4216 | | "bindkey_o", |
4217 | | " ", |
4218 | | 3, |
4219 | | 0, |
4220 | | 0, |
4221 | | 0, |
4222 | | 0, |
4223 | | 0, |
4224 | | 0, |
4225 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4226 | | }, |
4227 | | { |
4228 | | MVM_OP_existskey, |
4229 | | "existskey", |
4230 | | " ", |
4231 | | 3, |
4232 | | 1, |
4233 | | 0, |
4234 | | 0, |
4235 | | 0, |
4236 | | 0, |
4237 | | 0, |
4238 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4239 | | }, |
4240 | | { |
4241 | | MVM_OP_deletekey, |
4242 | | "deletekey", |
4243 | | " ", |
4244 | | 2, |
4245 | | 0, |
4246 | | 0, |
4247 | | 0, |
4248 | | 0, |
4249 | | 0, |
4250 | | 0, |
4251 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4252 | | }, |
4253 | | { |
4254 | | MVM_OP_elems, |
4255 | | "elems", |
4256 | | " ", |
4257 | | 2, |
4258 | | 1, |
4259 | | 0, |
4260 | | 0, |
4261 | | 0, |
4262 | | 0, |
4263 | | 0, |
4264 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4265 | | }, |
4266 | | { |
4267 | | MVM_OP_knowhow, |
4268 | | "knowhow", |
4269 | | " ", |
4270 | | 1, |
4271 | | 1, |
4272 | | 0, |
4273 | | 0, |
4274 | | 0, |
4275 | | 0, |
4276 | | 0, |
4277 | | { MVM_operand_write_reg | MVM_operand_obj } |
4278 | | }, |
4279 | | { |
4280 | | MVM_OP_knowhowattr, |
4281 | | "knowhowattr", |
4282 | | " ", |
4283 | | 1, |
4284 | | 1, |
4285 | | 0, |
4286 | | 0, |
4287 | | 0, |
4288 | | 0, |
4289 | | 0, |
4290 | | { MVM_operand_write_reg | MVM_operand_obj } |
4291 | | }, |
4292 | | { |
4293 | | MVM_OP_newtype, |
4294 | | "newtype", |
4295 | | " ", |
4296 | | 3, |
4297 | | 0, |
4298 | | 0, |
4299 | | 0, |
4300 | | 0, |
4301 | | 0, |
4302 | | 0, |
4303 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4304 | | }, |
4305 | | { |
4306 | | MVM_OP_composetype, |
4307 | | "composetype", |
4308 | | " ", |
4309 | | 3, |
4310 | | 0, |
4311 | | 0, |
4312 | | 0, |
4313 | | 0, |
4314 | | 0, |
4315 | | 0, |
4316 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4317 | | }, |
4318 | | { |
4319 | | MVM_OP_setmethcache, |
4320 | | "setmethcache", |
4321 | | " ", |
4322 | | 2, |
4323 | | 0, |
4324 | | 0, |
4325 | | 0, |
4326 | | 0, |
4327 | | 0, |
4328 | | 0, |
4329 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4330 | | }, |
4331 | | { |
4332 | | MVM_OP_setmethcacheauth, |
4333 | | "setmethcacheauth", |
4334 | | " ", |
4335 | | 2, |
4336 | | 0, |
4337 | | 0, |
4338 | | 0, |
4339 | | 0, |
4340 | | 0, |
4341 | | 0, |
4342 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
4343 | | }, |
4344 | | { |
4345 | | MVM_OP_settypecache, |
4346 | | "settypecache", |
4347 | | " ", |
4348 | | 2, |
4349 | | 0, |
4350 | | 0, |
4351 | | 0, |
4352 | | 0, |
4353 | | 0, |
4354 | | 0, |
4355 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4356 | | }, |
4357 | | { |
4358 | | MVM_OP_settypecheckmode, |
4359 | | "settypecheckmode", |
4360 | | " ", |
4361 | | 2, |
4362 | | 0, |
4363 | | 0, |
4364 | | 0, |
4365 | | 0, |
4366 | | 0, |
4367 | | 0, |
4368 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
4369 | | }, |
4370 | | { |
4371 | | MVM_OP_setboolspec, |
4372 | | "setboolspec", |
4373 | | " ", |
4374 | | 3, |
4375 | | 0, |
4376 | | 0, |
4377 | | 0, |
4378 | | 0, |
4379 | | 0, |
4380 | | 0, |
4381 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4382 | | }, |
4383 | | { |
4384 | | MVM_OP_istrue, |
4385 | | "istrue", |
4386 | | " ", |
4387 | | 2, |
4388 | | 0, |
4389 | | 0, |
4390 | | 0, |
4391 | | 0, |
4392 | | 1, |
4393 | | 0, |
4394 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4395 | | }, |
4396 | | { |
4397 | | MVM_OP_isfalse, |
4398 | | "isfalse", |
4399 | | " ", |
4400 | | 2, |
4401 | | 0, |
4402 | | 0, |
4403 | | 0, |
4404 | | 0, |
4405 | | 1, |
4406 | | 0, |
4407 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4408 | | }, |
4409 | | { |
4410 | | MVM_OP_bootint, |
4411 | | "bootint", |
4412 | | " ", |
4413 | | 1, |
4414 | | 1, |
4415 | | 0, |
4416 | | 0, |
4417 | | 0, |
4418 | | 0, |
4419 | | 0, |
4420 | | { MVM_operand_write_reg | MVM_operand_obj } |
4421 | | }, |
4422 | | { |
4423 | | MVM_OP_bootnum, |
4424 | | "bootnum", |
4425 | | " ", |
4426 | | 1, |
4427 | | 1, |
4428 | | 0, |
4429 | | 0, |
4430 | | 0, |
4431 | | 0, |
4432 | | 0, |
4433 | | { MVM_operand_write_reg | MVM_operand_obj } |
4434 | | }, |
4435 | | { |
4436 | | MVM_OP_bootstr, |
4437 | | "bootstr", |
4438 | | " ", |
4439 | | 1, |
4440 | | 1, |
4441 | | 0, |
4442 | | 0, |
4443 | | 0, |
4444 | | 0, |
4445 | | 0, |
4446 | | { MVM_operand_write_reg | MVM_operand_obj } |
4447 | | }, |
4448 | | { |
4449 | | MVM_OP_bootarray, |
4450 | | "bootarray", |
4451 | | " ", |
4452 | | 1, |
4453 | | 1, |
4454 | | 0, |
4455 | | 0, |
4456 | | 0, |
4457 | | 0, |
4458 | | 0, |
4459 | | { MVM_operand_write_reg | MVM_operand_obj } |
4460 | | }, |
4461 | | { |
4462 | | MVM_OP_bootintarray, |
4463 | | "bootintarray", |
4464 | | " ", |
4465 | | 1, |
4466 | | 1, |
4467 | | 0, |
4468 | | 0, |
4469 | | 0, |
4470 | | 0, |
4471 | | 0, |
4472 | | { MVM_operand_write_reg | MVM_operand_obj } |
4473 | | }, |
4474 | | { |
4475 | | MVM_OP_bootnumarray, |
4476 | | "bootnumarray", |
4477 | | " ", |
4478 | | 1, |
4479 | | 1, |
4480 | | 0, |
4481 | | 0, |
4482 | | 0, |
4483 | | 0, |
4484 | | 0, |
4485 | | { MVM_operand_write_reg | MVM_operand_obj } |
4486 | | }, |
4487 | | { |
4488 | | MVM_OP_bootstrarray, |
4489 | | "bootstrarray", |
4490 | | " ", |
4491 | | 1, |
4492 | | 1, |
4493 | | 0, |
4494 | | 0, |
4495 | | 0, |
4496 | | 0, |
4497 | | 0, |
4498 | | { MVM_operand_write_reg | MVM_operand_obj } |
4499 | | }, |
4500 | | { |
4501 | | MVM_OP_boothash, |
4502 | | "boothash", |
4503 | | " ", |
4504 | | 1, |
4505 | | 1, |
4506 | | 0, |
4507 | | 0, |
4508 | | 0, |
4509 | | 0, |
4510 | | 0, |
4511 | | { MVM_operand_write_reg | MVM_operand_obj } |
4512 | | }, |
4513 | | { |
4514 | | MVM_OP_isint, |
4515 | | "isint", |
4516 | | " ", |
4517 | | 2, |
4518 | | 1, |
4519 | | 0, |
4520 | | 0, |
4521 | | 0, |
4522 | | 0, |
4523 | | 0, |
4524 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4525 | | }, |
4526 | | { |
4527 | | MVM_OP_isnum, |
4528 | | "isnum", |
4529 | | " ", |
4530 | | 2, |
4531 | | 1, |
4532 | | 0, |
4533 | | 0, |
4534 | | 0, |
4535 | | 0, |
4536 | | 0, |
4537 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4538 | | }, |
4539 | | { |
4540 | | MVM_OP_isstr, |
4541 | | "isstr", |
4542 | | " ", |
4543 | | 2, |
4544 | | 1, |
4545 | | 0, |
4546 | | 0, |
4547 | | 0, |
4548 | | 0, |
4549 | | 0, |
4550 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4551 | | }, |
4552 | | { |
4553 | | MVM_OP_islist, |
4554 | | "islist", |
4555 | | " ", |
4556 | | 2, |
4557 | | 1, |
4558 | | 0, |
4559 | | 0, |
4560 | | 0, |
4561 | | 0, |
4562 | | 0, |
4563 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4564 | | }, |
4565 | | { |
4566 | | MVM_OP_ishash, |
4567 | | "ishash", |
4568 | | " ", |
4569 | | 2, |
4570 | | 1, |
4571 | | 0, |
4572 | | 0, |
4573 | | 0, |
4574 | | 0, |
4575 | | 0, |
4576 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4577 | | }, |
4578 | | { |
4579 | | MVM_OP_sethllconfig, |
4580 | | "sethllconfig", |
4581 | | " ", |
4582 | | 2, |
4583 | | 0, |
4584 | | 0, |
4585 | | 0, |
4586 | | 0, |
4587 | | 0, |
4588 | | 0, |
4589 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4590 | | }, |
4591 | | { |
4592 | | MVM_OP_hllboxtype_i, |
4593 | | "hllboxtype_i", |
4594 | | " ", |
4595 | | 1, |
4596 | | 1, |
4597 | | 0, |
4598 | | 0, |
4599 | | 0, |
4600 | | 0, |
4601 | | 1, |
4602 | | { MVM_operand_write_reg | MVM_operand_obj } |
4603 | | }, |
4604 | | { |
4605 | | MVM_OP_hllboxtype_n, |
4606 | | "hllboxtype_n", |
4607 | | " ", |
4608 | | 1, |
4609 | | 1, |
4610 | | 0, |
4611 | | 0, |
4612 | | 0, |
4613 | | 0, |
4614 | | 1, |
4615 | | { MVM_operand_write_reg | MVM_operand_obj } |
4616 | | }, |
4617 | | { |
4618 | | MVM_OP_hllboxtype_s, |
4619 | | "hllboxtype_s", |
4620 | | " ", |
4621 | | 1, |
4622 | | 1, |
4623 | | 0, |
4624 | | 0, |
4625 | | 0, |
4626 | | 0, |
4627 | | 1, |
4628 | | { MVM_operand_write_reg | MVM_operand_obj } |
4629 | | }, |
4630 | | { |
4631 | | MVM_OP_hlllist, |
4632 | | "hlllist", |
4633 | | " ", |
4634 | | 1, |
4635 | | 1, |
4636 | | 0, |
4637 | | 0, |
4638 | | 0, |
4639 | | 0, |
4640 | | 1, |
4641 | | { MVM_operand_write_reg | MVM_operand_obj } |
4642 | | }, |
4643 | | { |
4644 | | MVM_OP_hllhash, |
4645 | | "hllhash", |
4646 | | " ", |
4647 | | 1, |
4648 | | 1, |
4649 | | 0, |
4650 | | 0, |
4651 | | 0, |
4652 | | 0, |
4653 | | 1, |
4654 | | { MVM_operand_write_reg | MVM_operand_obj } |
4655 | | }, |
4656 | | { |
4657 | | MVM_OP_getcomp, |
4658 | | "getcomp", |
4659 | | " ", |
4660 | | 2, |
4661 | | 1, |
4662 | | 0, |
4663 | | 0, |
4664 | | 0, |
4665 | | 0, |
4666 | | 0, |
4667 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4668 | | }, |
4669 | | { |
4670 | | MVM_OP_bindcomp, |
4671 | | "bindcomp", |
4672 | | " ", |
4673 | | 3, |
4674 | | 0, |
4675 | | 0, |
4676 | | 0, |
4677 | | 0, |
4678 | | 0, |
4679 | | 0, |
4680 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4681 | | }, |
4682 | | { |
4683 | | MVM_OP_getcurhllsym, |
4684 | | "getcurhllsym", |
4685 | | " ", |
4686 | | 2, |
4687 | | 1, |
4688 | | 0, |
4689 | | 0, |
4690 | | 0, |
4691 | | 0, |
4692 | | 1, |
4693 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4694 | | }, |
4695 | | { |
4696 | | MVM_OP_bindcurhllsym, |
4697 | | "bindcurhllsym", |
4698 | | " ", |
4699 | | 3, |
4700 | | 0, |
4701 | | 0, |
4702 | | 0, |
4703 | | 0, |
4704 | | 0, |
4705 | | 1, |
4706 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4707 | | }, |
4708 | | { |
4709 | | MVM_OP_gethllsym, |
4710 | | "gethllsym", |
4711 | | " ", |
4712 | | 3, |
4713 | | 1, |
4714 | | 0, |
4715 | | 0, |
4716 | | 0, |
4717 | | 0, |
4718 | | 0, |
4719 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
4720 | | }, |
4721 | | { |
4722 | | MVM_OP_bindhllsym, |
4723 | | "bindhllsym", |
4724 | | " ", |
4725 | | 3, |
4726 | | 0, |
4727 | | 0, |
4728 | | 0, |
4729 | | 0, |
4730 | | 0, |
4731 | | 0, |
4732 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4733 | | }, |
4734 | | { |
4735 | | MVM_OP_settypehll, |
4736 | | "settypehll", |
4737 | | " ", |
4738 | | 2, |
4739 | | 0, |
4740 | | 0, |
4741 | | 0, |
4742 | | 0, |
4743 | | 0, |
4744 | | 0, |
4745 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4746 | | }, |
4747 | | { |
4748 | | MVM_OP_settypehllrole, |
4749 | | "settypehllrole", |
4750 | | " ", |
4751 | | 2, |
4752 | | 0, |
4753 | | 0, |
4754 | | 0, |
4755 | | 0, |
4756 | | 0, |
4757 | | 0, |
4758 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
4759 | | }, |
4760 | | { |
4761 | | MVM_OP_hllize, |
4762 | | "hllize", |
4763 | | " ", |
4764 | | 2, |
4765 | | 1, |
4766 | | 0, |
4767 | | 0, |
4768 | | 0, |
4769 | | 1, |
4770 | | 1, |
4771 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4772 | | }, |
4773 | | { |
4774 | | MVM_OP_hllizefor, |
4775 | | "hllizefor", |
4776 | | " ", |
4777 | | 3, |
4778 | | 1, |
4779 | | 0, |
4780 | | 0, |
4781 | | 0, |
4782 | | 1, |
4783 | | 0, |
4784 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4785 | | }, |
4786 | | { |
4787 | | MVM_OP_usecompileehllconfig, |
4788 | | "usecompileehllconfig", |
4789 | | " ", |
4790 | | 0, |
4791 | | 0, |
4792 | | 0, |
4793 | | 0, |
4794 | | 0, |
4795 | | 0, |
4796 | | 1, |
4797 | | }, |
4798 | | { |
4799 | | MVM_OP_usecompilerhllconfig, |
4800 | | "usecompilerhllconfig", |
4801 | | " ", |
4802 | | 0, |
4803 | | 0, |
4804 | | 0, |
4805 | | 0, |
4806 | | 0, |
4807 | | 0, |
4808 | | 1, |
4809 | | }, |
4810 | | { |
4811 | | MVM_OP_iter, |
4812 | | "iter", |
4813 | | " ", |
4814 | | 2, |
4815 | | 1, |
4816 | | 0, |
4817 | | 0, |
4818 | | 0, |
4819 | | 0, |
4820 | | 1, |
4821 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4822 | | }, |
4823 | | { |
4824 | | MVM_OP_iterkey_s, |
4825 | | "iterkey_s", |
4826 | | " ", |
4827 | | 2, |
4828 | | 1, |
4829 | | 0, |
4830 | | 0, |
4831 | | 0, |
4832 | | 0, |
4833 | | 0, |
4834 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4835 | | }, |
4836 | | { |
4837 | | MVM_OP_iterval, |
4838 | | "iterval", |
4839 | | " ", |
4840 | | 2, |
4841 | | 1, |
4842 | | 0, |
4843 | | 0, |
4844 | | 0, |
4845 | | 0, |
4846 | | 0, |
4847 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4848 | | }, |
4849 | | { |
4850 | | MVM_OP_getcodename, |
4851 | | "getcodename", |
4852 | | " ", |
4853 | | 2, |
4854 | | 1, |
4855 | | 0, |
4856 | | 0, |
4857 | | 0, |
4858 | | 0, |
4859 | | 0, |
4860 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4861 | | }, |
4862 | | { |
4863 | | MVM_OP_iscoderef, |
4864 | | "iscoderef", |
4865 | | " ", |
4866 | | 2, |
4867 | | 1, |
4868 | | 0, |
4869 | | 0, |
4870 | | 0, |
4871 | | 0, |
4872 | | 0, |
4873 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4874 | | }, |
4875 | | { |
4876 | | MVM_OP_getcodeobj, |
4877 | | "getcodeobj", |
4878 | | " ", |
4879 | | 2, |
4880 | | 1, |
4881 | | 0, |
4882 | | 0, |
4883 | | 0, |
4884 | | 0, |
4885 | | 0, |
4886 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4887 | | }, |
4888 | | { |
4889 | | MVM_OP_setcodeobj, |
4890 | | "setcodeobj", |
4891 | | " ", |
4892 | | 2, |
4893 | | 0, |
4894 | | 0, |
4895 | | 0, |
4896 | | 0, |
4897 | | 0, |
4898 | | 0, |
4899 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4900 | | }, |
4901 | | { |
4902 | | MVM_OP_setcodename, |
4903 | | "setcodename", |
4904 | | " ", |
4905 | | 2, |
4906 | | 0, |
4907 | | 0, |
4908 | | 0, |
4909 | | 0, |
4910 | | 0, |
4911 | | 0, |
4912 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
4913 | | }, |
4914 | | { |
4915 | | MVM_OP_forceouterctx, |
4916 | | "forceouterctx", |
4917 | | " ", |
4918 | | 2, |
4919 | | 0, |
4920 | | 0, |
4921 | | 0, |
4922 | | 0, |
4923 | | 0, |
4924 | | 0, |
4925 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4926 | | }, |
4927 | | { |
4928 | | MVM_OP_setinvokespec, |
4929 | | "setinvokespec", |
4930 | | " ", |
4931 | | 4, |
4932 | | 0, |
4933 | | 0, |
4934 | | 0, |
4935 | | 0, |
4936 | | 0, |
4937 | | 0, |
4938 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
4939 | | }, |
4940 | | { |
4941 | | MVM_OP_isinvokable, |
4942 | | "isinvokable", |
4943 | | " ", |
4944 | | 2, |
4945 | | 1, |
4946 | | 0, |
4947 | | 0, |
4948 | | 0, |
4949 | | 0, |
4950 | | 0, |
4951 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
4952 | | }, |
4953 | | { |
4954 | | MVM_OP_freshcoderef, |
4955 | | "freshcoderef", |
4956 | | " ", |
4957 | | 2, |
4958 | | 0, |
4959 | | 0, |
4960 | | 0, |
4961 | | 0, |
4962 | | 0, |
4963 | | 0, |
4964 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
4965 | | }, |
4966 | | { |
4967 | | MVM_OP_markcodestatic, |
4968 | | "markcodestatic", |
4969 | | " ", |
4970 | | 1, |
4971 | | 0, |
4972 | | 0, |
4973 | | 0, |
4974 | | 0, |
4975 | | 0, |
4976 | | 0, |
4977 | | { MVM_operand_read_reg | MVM_operand_obj } |
4978 | | }, |
4979 | | { |
4980 | | MVM_OP_markcodestub, |
4981 | | "markcodestub", |
4982 | | " ", |
4983 | | 1, |
4984 | | 0, |
4985 | | 0, |
4986 | | 0, |
4987 | | 0, |
4988 | | 0, |
4989 | | 0, |
4990 | | { MVM_operand_read_reg | MVM_operand_obj } |
4991 | | }, |
4992 | | { |
4993 | | MVM_OP_getstaticcode, |
4994 | | "getstaticcode", |
4995 | | " ", |
4996 | | 2, |
4997 | | 1, |
4998 | | 0, |
4999 | | 0, |
5000 | | 0, |
5001 | | 0, |
5002 | | 0, |
5003 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5004 | | }, |
5005 | | { |
5006 | | MVM_OP_getcodecuid, |
5007 | | "getcodecuid", |
5008 | | " ", |
5009 | | 2, |
5010 | | 1, |
5011 | | 0, |
5012 | | 0, |
5013 | | 0, |
5014 | | 0, |
5015 | | 0, |
5016 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
5017 | | }, |
5018 | | { |
5019 | | MVM_OP_setdispatcher, |
5020 | | "setdispatcher", |
5021 | | " ", |
5022 | | 1, |
5023 | | 0, |
5024 | | 0, |
5025 | | 0, |
5026 | | 0, |
5027 | | 0, |
5028 | | 0, |
5029 | | { MVM_operand_read_reg | MVM_operand_obj } |
5030 | | }, |
5031 | | { |
5032 | | MVM_OP_takedispatcher, |
5033 | | "takedispatcher", |
5034 | | " ", |
5035 | | 1, |
5036 | | 0, |
5037 | | 0, |
5038 | | 0, |
5039 | | 0, |
5040 | | 0, |
5041 | | 0, |
5042 | | { MVM_operand_write_reg | MVM_operand_obj } |
5043 | | }, |
5044 | | { |
5045 | | MVM_OP_assign, |
5046 | | "assign", |
5047 | | " ", |
5048 | | 2, |
5049 | | 0, |
5050 | | 0, |
5051 | | 0, |
5052 | | 0, |
5053 | | 1, |
5054 | | 0, |
5055 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5056 | | }, |
5057 | | { |
5058 | | MVM_OP_assignunchecked, |
5059 | | "assignunchecked", |
5060 | | " ", |
5061 | | 2, |
5062 | | 0, |
5063 | | 0, |
5064 | | 0, |
5065 | | 0, |
5066 | | 1, |
5067 | | 0, |
5068 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5069 | | }, |
5070 | | { |
5071 | | MVM_OP_iscont, |
5072 | | "iscont", |
5073 | | " ", |
5074 | | 2, |
5075 | | 1, |
5076 | | 0, |
5077 | | 0, |
5078 | | 0, |
5079 | | 0, |
5080 | | 0, |
5081 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5082 | | }, |
5083 | | { |
5084 | | MVM_OP_decont, |
5085 | | "decont", |
5086 | | " ", |
5087 | | 2, |
5088 | | 1, |
5089 | | 1, |
5090 | | 0, |
5091 | | 0, |
5092 | | 1, |
5093 | | 0, |
5094 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5095 | | }, |
5096 | | { |
5097 | | MVM_OP_setcontspec, |
5098 | | "setcontspec", |
5099 | | " ", |
5100 | | 3, |
5101 | | 0, |
5102 | | 0, |
5103 | | 0, |
5104 | | 0, |
5105 | | 0, |
5106 | | 0, |
5107 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
5108 | | }, |
5109 | | { |
5110 | | MVM_OP_sha1, |
5111 | | "sha1", |
5112 | | " ", |
5113 | | 2, |
5114 | | 1, |
5115 | | 0, |
5116 | | 0, |
5117 | | 0, |
5118 | | 0, |
5119 | | 0, |
5120 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
5121 | | }, |
5122 | | { |
5123 | | MVM_OP_createsc, |
5124 | | "createsc", |
5125 | | " ", |
5126 | | 2, |
5127 | | 0, |
5128 | | 0, |
5129 | | 0, |
5130 | | 0, |
5131 | | 0, |
5132 | | 0, |
5133 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
5134 | | }, |
5135 | | { |
5136 | | MVM_OP_scsetobj, |
5137 | | "scsetobj", |
5138 | | " ", |
5139 | | 3, |
5140 | | 0, |
5141 | | 0, |
5142 | | 0, |
5143 | | 0, |
5144 | | 0, |
5145 | | 0, |
5146 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5147 | | }, |
5148 | | { |
5149 | | MVM_OP_scsetcode, |
5150 | | "scsetcode", |
5151 | | " ", |
5152 | | 3, |
5153 | | 0, |
5154 | | 0, |
5155 | | 0, |
5156 | | 0, |
5157 | | 0, |
5158 | | 0, |
5159 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5160 | | }, |
5161 | | { |
5162 | | MVM_OP_scgetobj, |
5163 | | "scgetobj", |
5164 | | " ", |
5165 | | 3, |
5166 | | 0, |
5167 | | 0, |
5168 | | 0, |
5169 | | 0, |
5170 | | 0, |
5171 | | 0, |
5172 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
5173 | | }, |
5174 | | { |
5175 | | MVM_OP_scgethandle, |
5176 | | "scgethandle", |
5177 | | " ", |
5178 | | 2, |
5179 | | 0, |
5180 | | 0, |
5181 | | 0, |
5182 | | 0, |
5183 | | 0, |
5184 | | 0, |
5185 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
5186 | | }, |
5187 | | { |
5188 | | MVM_OP_scgetobjidx, |
5189 | | "scgetobjidx", |
5190 | | " ", |
5191 | | 3, |
5192 | | 0, |
5193 | | 0, |
5194 | | 0, |
5195 | | 0, |
5196 | | 0, |
5197 | | 0, |
5198 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5199 | | }, |
5200 | | { |
5201 | | MVM_OP_scsetdesc, |
5202 | | "scsetdesc", |
5203 | | " ", |
5204 | | 2, |
5205 | | 0, |
5206 | | 0, |
5207 | | 0, |
5208 | | 0, |
5209 | | 0, |
5210 | | 0, |
5211 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
5212 | | }, |
5213 | | { |
5214 | | MVM_OP_scobjcount, |
5215 | | "scobjcount", |
5216 | | " ", |
5217 | | 2, |
5218 | | 0, |
5219 | | 0, |
5220 | | 0, |
5221 | | 0, |
5222 | | 0, |
5223 | | 0, |
5224 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5225 | | }, |
5226 | | { |
5227 | | MVM_OP_setobjsc, |
5228 | | "setobjsc", |
5229 | | " ", |
5230 | | 2, |
5231 | | 0, |
5232 | | 0, |
5233 | | 0, |
5234 | | 0, |
5235 | | 0, |
5236 | | 0, |
5237 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5238 | | }, |
5239 | | { |
5240 | | MVM_OP_getobjsc, |
5241 | | "getobjsc", |
5242 | | " ", |
5243 | | 2, |
5244 | | 0, |
5245 | | 0, |
5246 | | 0, |
5247 | | 0, |
5248 | | 0, |
5249 | | 0, |
5250 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5251 | | }, |
5252 | | { |
5253 | | MVM_OP_serialize, |
5254 | | "serialize", |
5255 | | " ", |
5256 | | 3, |
5257 | | 0, |
5258 | | 0, |
5259 | | 0, |
5260 | | 0, |
5261 | | 0, |
5262 | | 0, |
5263 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5264 | | }, |
5265 | | { |
5266 | | MVM_OP_deserialize, |
5267 | | "deserialize", |
5268 | | " ", |
5269 | | 5, |
5270 | | 0, |
5271 | | 0, |
5272 | | 0, |
5273 | | 0, |
5274 | | 0, |
5275 | | 0, |
5276 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5277 | | }, |
5278 | | { |
5279 | | MVM_OP_wval, |
5280 | | "wval", |
5281 | | " ", |
5282 | | 3, |
5283 | | 1, |
5284 | | 0, |
5285 | | 0, |
5286 | | 0, |
5287 | | 0, |
5288 | | 0, |
5289 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_int16 } |
5290 | | }, |
5291 | | { |
5292 | | MVM_OP_wval_wide, |
5293 | | "wval_wide", |
5294 | | " ", |
5295 | | 3, |
5296 | | 1, |
5297 | | 0, |
5298 | | 0, |
5299 | | 0, |
5300 | | 0, |
5301 | | 0, |
5302 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_int64 } |
5303 | | }, |
5304 | | { |
5305 | | MVM_OP_scwbdisable, |
5306 | | "scwbdisable", |
5307 | | " ", |
5308 | | 1, |
5309 | | 0, |
5310 | | 0, |
5311 | | 0, |
5312 | | 0, |
5313 | | 0, |
5314 | | 0, |
5315 | | { MVM_operand_write_reg | MVM_operand_int64 } |
5316 | | }, |
5317 | | { |
5318 | | MVM_OP_scwbenable, |
5319 | | "scwbenable", |
5320 | | " ", |
5321 | | 1, |
5322 | | 0, |
5323 | | 0, |
5324 | | 0, |
5325 | | 0, |
5326 | | 0, |
5327 | | 0, |
5328 | | { MVM_operand_write_reg | MVM_operand_int64 } |
5329 | | }, |
5330 | | { |
5331 | | MVM_OP_pushcompsc, |
5332 | | "pushcompsc", |
5333 | | " ", |
5334 | | 1, |
5335 | | 0, |
5336 | | 0, |
5337 | | 0, |
5338 | | 0, |
5339 | | 0, |
5340 | | 0, |
5341 | | { MVM_operand_read_reg | MVM_operand_obj } |
5342 | | }, |
5343 | | { |
5344 | | MVM_OP_popcompsc, |
5345 | | "popcompsc", |
5346 | | " ", |
5347 | | 1, |
5348 | | 0, |
5349 | | 0, |
5350 | | 0, |
5351 | | 0, |
5352 | | 0, |
5353 | | 0, |
5354 | | { MVM_operand_write_reg | MVM_operand_obj } |
5355 | | }, |
5356 | | { |
5357 | | MVM_OP_scgetdesc, |
5358 | | "scgetdesc", |
5359 | | " ", |
5360 | | 2, |
5361 | | 0, |
5362 | | 0, |
5363 | | 0, |
5364 | | 0, |
5365 | | 0, |
5366 | | 0, |
5367 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
5368 | | }, |
5369 | | { |
5370 | | MVM_OP_loadbytecode, |
5371 | | "loadbytecode", |
5372 | | " ", |
5373 | | 2, |
5374 | | 0, |
5375 | | 0, |
5376 | | 0, |
5377 | | 0, |
5378 | | 1, |
5379 | | 0, |
5380 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
5381 | | }, |
5382 | | { |
5383 | | MVM_OP_masttofile, |
5384 | | "masttofile", |
5385 | | " ", |
5386 | | 3, |
5387 | | 0, |
5388 | | 0, |
5389 | | 0, |
5390 | | 0, |
5391 | | 0, |
5392 | | 0, |
5393 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
5394 | | }, |
5395 | | { |
5396 | | MVM_OP_masttocu, |
5397 | | "masttocu", |
5398 | | " ", |
5399 | | 3, |
5400 | | 0, |
5401 | | 0, |
5402 | | 0, |
5403 | | 0, |
5404 | | 1, |
5405 | | 0, |
5406 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5407 | | }, |
5408 | | { |
5409 | | MVM_OP_iscompunit, |
5410 | | "iscompunit", |
5411 | | " ", |
5412 | | 2, |
5413 | | 1, |
5414 | | 0, |
5415 | | 0, |
5416 | | 0, |
5417 | | 0, |
5418 | | 0, |
5419 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5420 | | }, |
5421 | | { |
5422 | | MVM_OP_compunitmainline, |
5423 | | "compunitmainline", |
5424 | | " ", |
5425 | | 2, |
5426 | | 0, |
5427 | | 0, |
5428 | | 0, |
5429 | | 0, |
5430 | | 0, |
5431 | | 0, |
5432 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5433 | | }, |
5434 | | { |
5435 | | MVM_OP_compunitcodes, |
5436 | | "compunitcodes", |
5437 | | " ", |
5438 | | 2, |
5439 | | 0, |
5440 | | 0, |
5441 | | 0, |
5442 | | 0, |
5443 | | 0, |
5444 | | 0, |
5445 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5446 | | }, |
5447 | | { |
5448 | | MVM_OP_ctx, |
5449 | | "ctx", |
5450 | | " ", |
5451 | | 1, |
5452 | | 0, |
5453 | | 0, |
5454 | | 0, |
5455 | | 1, |
5456 | | 0, |
5457 | | 0, |
5458 | | { MVM_operand_write_reg | MVM_operand_obj } |
5459 | | }, |
5460 | | { |
5461 | | MVM_OP_ctxouter, |
5462 | | "ctxouter", |
5463 | | " ", |
5464 | | 2, |
5465 | | 0, |
5466 | | 0, |
5467 | | 0, |
5468 | | 0, |
5469 | | 0, |
5470 | | 0, |
5471 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5472 | | }, |
5473 | | { |
5474 | | MVM_OP_ctxcaller, |
5475 | | "ctxcaller", |
5476 | | " ", |
5477 | | 2, |
5478 | | 0, |
5479 | | 0, |
5480 | | 0, |
5481 | | 0, |
5482 | | 0, |
5483 | | 0, |
5484 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5485 | | }, |
5486 | | { |
5487 | | MVM_OP_ctxlexpad, |
5488 | | "ctxlexpad", |
5489 | | " ", |
5490 | | 2, |
5491 | | 0, |
5492 | | 0, |
5493 | | 0, |
5494 | | 0, |
5495 | | 0, |
5496 | | 0, |
5497 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5498 | | }, |
5499 | | { |
5500 | | MVM_OP_curcode, |
5501 | | "curcode", |
5502 | | " ", |
5503 | | 1, |
5504 | | 0, |
5505 | | 0, |
5506 | | 0, |
5507 | | 1, |
5508 | | 0, |
5509 | | 0, |
5510 | | { MVM_operand_write_reg | MVM_operand_obj } |
5511 | | }, |
5512 | | { |
5513 | | MVM_OP_callercode, |
5514 | | "callercode", |
5515 | | " ", |
5516 | | 1, |
5517 | | 0, |
5518 | | 0, |
5519 | | 0, |
5520 | | 1, |
5521 | | 0, |
5522 | | 0, |
5523 | | { MVM_operand_write_reg | MVM_operand_obj } |
5524 | | }, |
5525 | | { |
5526 | | MVM_OP_add_I, |
5527 | | "add_I", |
5528 | | " ", |
5529 | | 4, |
5530 | | 1, |
5531 | | 0, |
5532 | | 0, |
5533 | | 0, |
5534 | | 0, |
5535 | | 0, |
5536 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5537 | | }, |
5538 | | { |
5539 | | MVM_OP_sub_I, |
5540 | | "sub_I", |
5541 | | " ", |
5542 | | 4, |
5543 | | 1, |
5544 | | 0, |
5545 | | 0, |
5546 | | 0, |
5547 | | 0, |
5548 | | 0, |
5549 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5550 | | }, |
5551 | | { |
5552 | | MVM_OP_mul_I, |
5553 | | "mul_I", |
5554 | | " ", |
5555 | | 4, |
5556 | | 1, |
5557 | | 0, |
5558 | | 0, |
5559 | | 0, |
5560 | | 0, |
5561 | | 0, |
5562 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5563 | | }, |
5564 | | { |
5565 | | MVM_OP_div_I, |
5566 | | "div_I", |
5567 | | " ", |
5568 | | 4, |
5569 | | 1, |
5570 | | 0, |
5571 | | 0, |
5572 | | 0, |
5573 | | 0, |
5574 | | 0, |
5575 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5576 | | }, |
5577 | | { |
5578 | | MVM_OP_mod_I, |
5579 | | "mod_I", |
5580 | | " ", |
5581 | | 4, |
5582 | | 1, |
5583 | | 0, |
5584 | | 0, |
5585 | | 0, |
5586 | | 0, |
5587 | | 0, |
5588 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5589 | | }, |
5590 | | { |
5591 | | MVM_OP_neg_I, |
5592 | | "neg_I", |
5593 | | " ", |
5594 | | 3, |
5595 | | 1, |
5596 | | 0, |
5597 | | 0, |
5598 | | 0, |
5599 | | 0, |
5600 | | 0, |
5601 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5602 | | }, |
5603 | | { |
5604 | | MVM_OP_abs_I, |
5605 | | "abs_I", |
5606 | | " ", |
5607 | | 3, |
5608 | | 1, |
5609 | | 0, |
5610 | | 0, |
5611 | | 0, |
5612 | | 0, |
5613 | | 0, |
5614 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5615 | | }, |
5616 | | { |
5617 | | MVM_OP_cmp_I, |
5618 | | "cmp_I", |
5619 | | " ", |
5620 | | 3, |
5621 | | 1, |
5622 | | 0, |
5623 | | 0, |
5624 | | 0, |
5625 | | 0, |
5626 | | 0, |
5627 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5628 | | }, |
5629 | | { |
5630 | | MVM_OP_eq_I, |
5631 | | "eq_I", |
5632 | | " ", |
5633 | | 3, |
5634 | | 1, |
5635 | | 0, |
5636 | | 0, |
5637 | | 0, |
5638 | | 0, |
5639 | | 0, |
5640 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5641 | | }, |
5642 | | { |
5643 | | MVM_OP_ne_I, |
5644 | | "ne_I", |
5645 | | " ", |
5646 | | 3, |
5647 | | 1, |
5648 | | 0, |
5649 | | 0, |
5650 | | 0, |
5651 | | 0, |
5652 | | 0, |
5653 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5654 | | }, |
5655 | | { |
5656 | | MVM_OP_lt_I, |
5657 | | "lt_I", |
5658 | | " ", |
5659 | | 3, |
5660 | | 1, |
5661 | | 0, |
5662 | | 0, |
5663 | | 0, |
5664 | | 0, |
5665 | | 0, |
5666 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5667 | | }, |
5668 | | { |
5669 | | MVM_OP_le_I, |
5670 | | "le_I", |
5671 | | " ", |
5672 | | 3, |
5673 | | 1, |
5674 | | 0, |
5675 | | 0, |
5676 | | 0, |
5677 | | 0, |
5678 | | 0, |
5679 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5680 | | }, |
5681 | | { |
5682 | | MVM_OP_gt_I, |
5683 | | "gt_I", |
5684 | | " ", |
5685 | | 3, |
5686 | | 1, |
5687 | | 0, |
5688 | | 0, |
5689 | | 0, |
5690 | | 0, |
5691 | | 0, |
5692 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5693 | | }, |
5694 | | { |
5695 | | MVM_OP_ge_I, |
5696 | | "ge_I", |
5697 | | " ", |
5698 | | 3, |
5699 | | 1, |
5700 | | 0, |
5701 | | 0, |
5702 | | 0, |
5703 | | 0, |
5704 | | 0, |
5705 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5706 | | }, |
5707 | | { |
5708 | | MVM_OP_bor_I, |
5709 | | "bor_I", |
5710 | | " ", |
5711 | | 4, |
5712 | | 1, |
5713 | | 0, |
5714 | | 0, |
5715 | | 0, |
5716 | | 0, |
5717 | | 0, |
5718 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5719 | | }, |
5720 | | { |
5721 | | MVM_OP_bxor_I, |
5722 | | "bxor_I", |
5723 | | " ", |
5724 | | 4, |
5725 | | 1, |
5726 | | 0, |
5727 | | 0, |
5728 | | 0, |
5729 | | 0, |
5730 | | 0, |
5731 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5732 | | }, |
5733 | | { |
5734 | | MVM_OP_band_I, |
5735 | | "band_I", |
5736 | | " ", |
5737 | | 4, |
5738 | | 1, |
5739 | | 0, |
5740 | | 0, |
5741 | | 0, |
5742 | | 0, |
5743 | | 0, |
5744 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5745 | | }, |
5746 | | { |
5747 | | MVM_OP_bnot_I, |
5748 | | "bnot_I", |
5749 | | " ", |
5750 | | 3, |
5751 | | 1, |
5752 | | 0, |
5753 | | 0, |
5754 | | 0, |
5755 | | 0, |
5756 | | 0, |
5757 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5758 | | }, |
5759 | | { |
5760 | | MVM_OP_blshift_I, |
5761 | | "blshift_I", |
5762 | | " ", |
5763 | | 4, |
5764 | | 1, |
5765 | | 0, |
5766 | | 0, |
5767 | | 0, |
5768 | | 0, |
5769 | | 0, |
5770 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5771 | | }, |
5772 | | { |
5773 | | MVM_OP_brshift_I, |
5774 | | "brshift_I", |
5775 | | " ", |
5776 | | 4, |
5777 | | 1, |
5778 | | 0, |
5779 | | 0, |
5780 | | 0, |
5781 | | 0, |
5782 | | 0, |
5783 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5784 | | }, |
5785 | | { |
5786 | | MVM_OP_pow_I, |
5787 | | "pow_I", |
5788 | | " ", |
5789 | | 5, |
5790 | | 1, |
5791 | | 0, |
5792 | | 0, |
5793 | | 0, |
5794 | | 0, |
5795 | | 0, |
5796 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5797 | | }, |
5798 | | { |
5799 | | MVM_OP_gcd_I, |
5800 | | "gcd_I", |
5801 | | " ", |
5802 | | 4, |
5803 | | 1, |
5804 | | 0, |
5805 | | 0, |
5806 | | 0, |
5807 | | 0, |
5808 | | 0, |
5809 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5810 | | }, |
5811 | | { |
5812 | | MVM_OP_lcm_I, |
5813 | | "lcm_I", |
5814 | | " ", |
5815 | | 4, |
5816 | | 1, |
5817 | | 0, |
5818 | | 0, |
5819 | | 0, |
5820 | | 0, |
5821 | | 0, |
5822 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5823 | | }, |
5824 | | { |
5825 | | MVM_OP_expmod_I, |
5826 | | "expmod_I", |
5827 | | " ", |
5828 | | 5, |
5829 | | 1, |
5830 | | 0, |
5831 | | 0, |
5832 | | 0, |
5833 | | 0, |
5834 | | 0, |
5835 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5836 | | }, |
5837 | | { |
5838 | | MVM_OP_isprime_I, |
5839 | | "isprime_I", |
5840 | | " ", |
5841 | | 3, |
5842 | | 1, |
5843 | | 0, |
5844 | | 0, |
5845 | | 0, |
5846 | | 0, |
5847 | | 0, |
5848 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
5849 | | }, |
5850 | | { |
5851 | | MVM_OP_rand_I, |
5852 | | "rand_I", |
5853 | | " ", |
5854 | | 3, |
5855 | | 1, |
5856 | | 0, |
5857 | | 0, |
5858 | | 0, |
5859 | | 0, |
5860 | | 0, |
5861 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5862 | | }, |
5863 | | { |
5864 | | MVM_OP_coerce_In, |
5865 | | "coerce_In", |
5866 | | " ", |
5867 | | 2, |
5868 | | 1, |
5869 | | 0, |
5870 | | 0, |
5871 | | 0, |
5872 | | 0, |
5873 | | 0, |
5874 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
5875 | | }, |
5876 | | { |
5877 | | MVM_OP_coerce_Is, |
5878 | | "coerce_Is", |
5879 | | " ", |
5880 | | 2, |
5881 | | 1, |
5882 | | 0, |
5883 | | 0, |
5884 | | 0, |
5885 | | 0, |
5886 | | 0, |
5887 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
5888 | | }, |
5889 | | { |
5890 | | MVM_OP_coerce_nI, |
5891 | | "coerce_nI", |
5892 | | " ", |
5893 | | 3, |
5894 | | 1, |
5895 | | 0, |
5896 | | 0, |
5897 | | 0, |
5898 | | 0, |
5899 | | 0, |
5900 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
5901 | | }, |
5902 | | { |
5903 | | MVM_OP_coerce_sI, |
5904 | | "coerce_sI", |
5905 | | " ", |
5906 | | 3, |
5907 | | 1, |
5908 | | 0, |
5909 | | 0, |
5910 | | 0, |
5911 | | 0, |
5912 | | 0, |
5913 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
5914 | | }, |
5915 | | { |
5916 | | MVM_OP_isbig_I, |
5917 | | "isbig_I", |
5918 | | " ", |
5919 | | 2, |
5920 | | 1, |
5921 | | 0, |
5922 | | 0, |
5923 | | 0, |
5924 | | 0, |
5925 | | 0, |
5926 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5927 | | }, |
5928 | | { |
5929 | | MVM_OP_bool_I, |
5930 | | "bool_I", |
5931 | | " ", |
5932 | | 2, |
5933 | | 1, |
5934 | | 0, |
5935 | | 0, |
5936 | | 0, |
5937 | | 0, |
5938 | | 0, |
5939 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5940 | | }, |
5941 | | { |
5942 | | MVM_OP_base_I, |
5943 | | "base_I", |
5944 | | " ", |
5945 | | 3, |
5946 | | 1, |
5947 | | 0, |
5948 | | 0, |
5949 | | 0, |
5950 | | 0, |
5951 | | 0, |
5952 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
5953 | | }, |
5954 | | { |
5955 | | MVM_OP_radix_I, |
5956 | | "radix_I", |
5957 | | " ", |
5958 | | 6, |
5959 | | 1, |
5960 | | 0, |
5961 | | 0, |
5962 | | 0, |
5963 | | 0, |
5964 | | 1, |
5965 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
5966 | | }, |
5967 | | { |
5968 | | MVM_OP_div_In, |
5969 | | "div_In", |
5970 | | " ", |
5971 | | 3, |
5972 | | 1, |
5973 | | 0, |
5974 | | 0, |
5975 | | 0, |
5976 | | 0, |
5977 | | 0, |
5978 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
5979 | | }, |
5980 | | { |
5981 | | MVM_OP_copy_f, |
5982 | | "copy_f", |
5983 | | " ", |
5984 | | 2, |
5985 | | 0, |
5986 | | 0, |
5987 | | 0, |
5988 | | 0, |
5989 | | 0, |
5990 | | 0, |
5991 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
5992 | | }, |
5993 | | { |
5994 | | MVM_OP_append_f, |
5995 | | "append_f", |
5996 | | " ", |
5997 | | 2, |
5998 | | 0, |
5999 | | 0, |
6000 | | 0, |
6001 | | 0, |
6002 | | 0, |
6003 | | 0, |
6004 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6005 | | }, |
6006 | | { |
6007 | | MVM_OP_rename_f, |
6008 | | "rename_f", |
6009 | | " ", |
6010 | | 2, |
6011 | | 0, |
6012 | | 0, |
6013 | | 0, |
6014 | | 0, |
6015 | | 0, |
6016 | | 0, |
6017 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6018 | | }, |
6019 | | { |
6020 | | MVM_OP_delete_f, |
6021 | | "delete_f", |
6022 | | " ", |
6023 | | 1, |
6024 | | 0, |
6025 | | 0, |
6026 | | 0, |
6027 | | 0, |
6028 | | 0, |
6029 | | 0, |
6030 | | { MVM_operand_read_reg | MVM_operand_str } |
6031 | | }, |
6032 | | { |
6033 | | MVM_OP_chmod_f, |
6034 | | "chmod_f", |
6035 | | " ", |
6036 | | 2, |
6037 | | 0, |
6038 | | 0, |
6039 | | 0, |
6040 | | 0, |
6041 | | 0, |
6042 | | 0, |
6043 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
6044 | | }, |
6045 | | { |
6046 | | MVM_OP_exists_f, |
6047 | | "exists_f", |
6048 | | " ", |
6049 | | 2, |
6050 | | 0, |
6051 | | 0, |
6052 | | 0, |
6053 | | 0, |
6054 | | 0, |
6055 | | 0, |
6056 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
6057 | | }, |
6058 | | { |
6059 | | MVM_OP_mkdir, |
6060 | | "mkdir", |
6061 | | " ", |
6062 | | 2, |
6063 | | 0, |
6064 | | 0, |
6065 | | 0, |
6066 | | 0, |
6067 | | 0, |
6068 | | 0, |
6069 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
6070 | | }, |
6071 | | { |
6072 | | MVM_OP_rmdir, |
6073 | | "rmdir", |
6074 | | " ", |
6075 | | 1, |
6076 | | 0, |
6077 | | 0, |
6078 | | 0, |
6079 | | 0, |
6080 | | 0, |
6081 | | 0, |
6082 | | { MVM_operand_read_reg | MVM_operand_str } |
6083 | | }, |
6084 | | { |
6085 | | MVM_OP_open_dir, |
6086 | | "open_dir", |
6087 | | " ", |
6088 | | 2, |
6089 | | 0, |
6090 | | 0, |
6091 | | 0, |
6092 | | 0, |
6093 | | 0, |
6094 | | 0, |
6095 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6096 | | }, |
6097 | | { |
6098 | | MVM_OP_read_dir, |
6099 | | "read_dir", |
6100 | | " ", |
6101 | | 2, |
6102 | | 0, |
6103 | | 0, |
6104 | | 0, |
6105 | | 0, |
6106 | | 0, |
6107 | | 0, |
6108 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
6109 | | }, |
6110 | | { |
6111 | | MVM_OP_close_dir, |
6112 | | "close_dir", |
6113 | | " ", |
6114 | | 1, |
6115 | | 0, |
6116 | | 0, |
6117 | | 0, |
6118 | | 0, |
6119 | | 0, |
6120 | | 0, |
6121 | | { MVM_operand_read_reg | MVM_operand_obj } |
6122 | | }, |
6123 | | { |
6124 | | MVM_OP_open_fh, |
6125 | | "open_fh", |
6126 | | " ", |
6127 | | 3, |
6128 | | 0, |
6129 | | 0, |
6130 | | 0, |
6131 | | 0, |
6132 | | 0, |
6133 | | 0, |
6134 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6135 | | }, |
6136 | | { |
6137 | | MVM_OP_close_fh, |
6138 | | "close_fh", |
6139 | | " ", |
6140 | | 1, |
6141 | | 0, |
6142 | | 0, |
6143 | | 0, |
6144 | | 0, |
6145 | | 0, |
6146 | | 0, |
6147 | | { MVM_operand_read_reg | MVM_operand_obj } |
6148 | | }, |
6149 | | { |
6150 | | MVM_OP_DEPRECATED_23, |
6151 | | "DEPRECATED_23", |
6152 | | " ", |
6153 | | 3, |
6154 | | 0, |
6155 | | 0, |
6156 | | 0, |
6157 | | 0, |
6158 | | 0, |
6159 | | 0, |
6160 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6161 | | }, |
6162 | | { |
6163 | | MVM_OP_DEPRECATED_27, |
6164 | | "DEPRECATED_27", |
6165 | | " ", |
6166 | | 3, |
6167 | | 0, |
6168 | | 0, |
6169 | | 0, |
6170 | | 0, |
6171 | | 0, |
6172 | | 0, |
6173 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6174 | | }, |
6175 | | { |
6176 | | MVM_OP_DEPRECATED_28, |
6177 | | "DEPRECATED_28", |
6178 | | " ", |
6179 | | 3, |
6180 | | 0, |
6181 | | 0, |
6182 | | 0, |
6183 | | 0, |
6184 | | 0, |
6185 | | 0, |
6186 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6187 | | }, |
6188 | | { |
6189 | | MVM_OP_DEPRECATED_18, |
6190 | | "DEPRECATED_18", |
6191 | | " ", |
6192 | | 3, |
6193 | | 0, |
6194 | | 0, |
6195 | | 0, |
6196 | | 0, |
6197 | | 0, |
6198 | | 0, |
6199 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6200 | | }, |
6201 | | { |
6202 | | MVM_OP_seek_fh, |
6203 | | "seek_fh", |
6204 | | " ", |
6205 | | 3, |
6206 | | 0, |
6207 | | 0, |
6208 | | 0, |
6209 | | 0, |
6210 | | 0, |
6211 | | 0, |
6212 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
6213 | | }, |
6214 | | { |
6215 | | MVM_OP_lock_fh, |
6216 | | "lock_fh", |
6217 | | " ", |
6218 | | 3, |
6219 | | 0, |
6220 | | 0, |
6221 | | 0, |
6222 | | 0, |
6223 | | 0, |
6224 | | 0, |
6225 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6226 | | }, |
6227 | | { |
6228 | | MVM_OP_unlock_fh, |
6229 | | "unlock_fh", |
6230 | | " ", |
6231 | | 1, |
6232 | | 0, |
6233 | | 0, |
6234 | | 0, |
6235 | | 0, |
6236 | | 0, |
6237 | | 0, |
6238 | | { MVM_operand_read_reg | MVM_operand_obj } |
6239 | | }, |
6240 | | { |
6241 | | MVM_OP_sync_fh, |
6242 | | "sync_fh", |
6243 | | " ", |
6244 | | 1, |
6245 | | 0, |
6246 | | 0, |
6247 | | 0, |
6248 | | 0, |
6249 | | 0, |
6250 | | 0, |
6251 | | { MVM_operand_read_reg | MVM_operand_obj } |
6252 | | }, |
6253 | | { |
6254 | | MVM_OP_trunc_fh, |
6255 | | "trunc_fh", |
6256 | | " ", |
6257 | | 2, |
6258 | | 0, |
6259 | | 0, |
6260 | | 0, |
6261 | | 0, |
6262 | | 0, |
6263 | | 0, |
6264 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6265 | | }, |
6266 | | { |
6267 | | MVM_OP_eof_fh, |
6268 | | "eof_fh", |
6269 | | " ", |
6270 | | 2, |
6271 | | 0, |
6272 | | 0, |
6273 | | 0, |
6274 | | 0, |
6275 | | 0, |
6276 | | 0, |
6277 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
6278 | | }, |
6279 | | { |
6280 | | MVM_OP_getstdin, |
6281 | | "getstdin", |
6282 | | " ", |
6283 | | 1, |
6284 | | 1, |
6285 | | 0, |
6286 | | 0, |
6287 | | 0, |
6288 | | 0, |
6289 | | 0, |
6290 | | { MVM_operand_write_reg | MVM_operand_obj } |
6291 | | }, |
6292 | | { |
6293 | | MVM_OP_getstdout, |
6294 | | "getstdout", |
6295 | | " ", |
6296 | | 1, |
6297 | | 1, |
6298 | | 0, |
6299 | | 0, |
6300 | | 0, |
6301 | | 0, |
6302 | | 0, |
6303 | | { MVM_operand_write_reg | MVM_operand_obj } |
6304 | | }, |
6305 | | { |
6306 | | MVM_OP_getstderr, |
6307 | | "getstderr", |
6308 | | " ", |
6309 | | 1, |
6310 | | 1, |
6311 | | 0, |
6312 | | 0, |
6313 | | 0, |
6314 | | 0, |
6315 | | 0, |
6316 | | { MVM_operand_write_reg | MVM_operand_obj } |
6317 | | }, |
6318 | | { |
6319 | | MVM_OP_connect_sk, |
6320 | | "connect_sk", |
6321 | | " ", |
6322 | | 3, |
6323 | | 0, |
6324 | | 0, |
6325 | | 0, |
6326 | | 0, |
6327 | | 0, |
6328 | | 0, |
6329 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
6330 | | }, |
6331 | | { |
6332 | | MVM_OP_socket, |
6333 | | "socket", |
6334 | | " ", |
6335 | | 2, |
6336 | | 0, |
6337 | | 0, |
6338 | | 0, |
6339 | | 0, |
6340 | | 0, |
6341 | | 0, |
6342 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6343 | | }, |
6344 | | { |
6345 | | MVM_OP_bind_sk, |
6346 | | "bind_sk", |
6347 | | " ", |
6348 | | 4, |
6349 | | 0, |
6350 | | 0, |
6351 | | 0, |
6352 | | 0, |
6353 | | 0, |
6354 | | 0, |
6355 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
6356 | | }, |
6357 | | { |
6358 | | MVM_OP_DEPRECATED_24, |
6359 | | "DEPRECATED_24", |
6360 | | " ", |
6361 | | 2, |
6362 | | 0, |
6363 | | 0, |
6364 | | 0, |
6365 | | 0, |
6366 | | 0, |
6367 | | 0, |
6368 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6369 | | }, |
6370 | | { |
6371 | | MVM_OP_accept_sk, |
6372 | | "accept_sk", |
6373 | | " ", |
6374 | | 2, |
6375 | | 0, |
6376 | | 0, |
6377 | | 0, |
6378 | | 0, |
6379 | | 0, |
6380 | | 0, |
6381 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
6382 | | }, |
6383 | | { |
6384 | | MVM_OP_decodetocodes, |
6385 | | "decodetocodes", |
6386 | | " ", |
6387 | | 4, |
6388 | | 0, |
6389 | | 0, |
6390 | | 0, |
6391 | | 0, |
6392 | | 0, |
6393 | | 0, |
6394 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
6395 | | }, |
6396 | | { |
6397 | | MVM_OP_encodefromcodes, |
6398 | | "encodefromcodes", |
6399 | | " ", |
6400 | | 3, |
6401 | | 0, |
6402 | | 0, |
6403 | | 0, |
6404 | | 0, |
6405 | | 0, |
6406 | | 0, |
6407 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
6408 | | }, |
6409 | | { |
6410 | | MVM_OP_DEPRECATED_17, |
6411 | | "DEPRECATED_17", |
6412 | | " ", |
6413 | | 2, |
6414 | | 0, |
6415 | | 0, |
6416 | | 0, |
6417 | | 0, |
6418 | | 0, |
6419 | | 0, |
6420 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6421 | | }, |
6422 | | { |
6423 | | MVM_OP_print, |
6424 | | "print", |
6425 | | " ", |
6426 | | 1, |
6427 | | 0, |
6428 | | 0, |
6429 | | 0, |
6430 | | 0, |
6431 | | 0, |
6432 | | 0, |
6433 | | { MVM_operand_read_reg | MVM_operand_str } |
6434 | | }, |
6435 | | { |
6436 | | MVM_OP_say, |
6437 | | "say", |
6438 | | " ", |
6439 | | 1, |
6440 | | 0, |
6441 | | 0, |
6442 | | 0, |
6443 | | 0, |
6444 | | 0, |
6445 | | 0, |
6446 | | { MVM_operand_read_reg | MVM_operand_str } |
6447 | | }, |
6448 | | { |
6449 | | MVM_OP_DEPRECATED_22, |
6450 | | "DEPRECATED_22", |
6451 | | " ", |
6452 | | 2, |
6453 | | 0, |
6454 | | 0, |
6455 | | 0, |
6456 | | 0, |
6457 | | 0, |
6458 | | 0, |
6459 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
6460 | | }, |
6461 | | { |
6462 | | MVM_OP_tell_fh, |
6463 | | "tell_fh", |
6464 | | " ", |
6465 | | 2, |
6466 | | 0, |
6467 | | 0, |
6468 | | 0, |
6469 | | 0, |
6470 | | 0, |
6471 | | 0, |
6472 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
6473 | | }, |
6474 | | { |
6475 | | MVM_OP_stat, |
6476 | | "stat", |
6477 | | " ", |
6478 | | 3, |
6479 | | 0, |
6480 | | 0, |
6481 | | 0, |
6482 | | 0, |
6483 | | 0, |
6484 | | 0, |
6485 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
6486 | | }, |
6487 | | { |
6488 | | MVM_OP_tryfindmeth, |
6489 | | "tryfindmeth", |
6490 | | " ", |
6491 | | 3, |
6492 | | 1, |
6493 | | 0, |
6494 | | 0, |
6495 | | 0, |
6496 | | 1, |
6497 | | 0, |
6498 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str } |
6499 | | }, |
6500 | | { |
6501 | | MVM_OP_tryfindmeth_s, |
6502 | | "tryfindmeth_s", |
6503 | | " ", |
6504 | | 3, |
6505 | | 1, |
6506 | | 0, |
6507 | | 0, |
6508 | | 0, |
6509 | | 1, |
6510 | | 0, |
6511 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6512 | | }, |
6513 | | { |
6514 | | MVM_OP_chdir, |
6515 | | "chdir", |
6516 | | " ", |
6517 | | 1, |
6518 | | 0, |
6519 | | 0, |
6520 | | 0, |
6521 | | 0, |
6522 | | 0, |
6523 | | 0, |
6524 | | { MVM_operand_read_reg | MVM_operand_str } |
6525 | | }, |
6526 | | { |
6527 | | MVM_OP_srand, |
6528 | | "srand", |
6529 | | " ", |
6530 | | 1, |
6531 | | 0, |
6532 | | 0, |
6533 | | 0, |
6534 | | 0, |
6535 | | 0, |
6536 | | 0, |
6537 | | { MVM_operand_read_reg | MVM_operand_int64 } |
6538 | | }, |
6539 | | { |
6540 | | MVM_OP_rand_i, |
6541 | | "rand_i", |
6542 | | " ", |
6543 | | 1, |
6544 | | 0, |
6545 | | 0, |
6546 | | 0, |
6547 | | 0, |
6548 | | 0, |
6549 | | 0, |
6550 | | { MVM_operand_write_reg | MVM_operand_int64 } |
6551 | | }, |
6552 | | { |
6553 | | MVM_OP_rand_n, |
6554 | | "rand_n", |
6555 | | " ", |
6556 | | 1, |
6557 | | 0, |
6558 | | 0, |
6559 | | 0, |
6560 | | 0, |
6561 | | 0, |
6562 | | 0, |
6563 | | { MVM_operand_write_reg | MVM_operand_num64 } |
6564 | | }, |
6565 | | { |
6566 | | MVM_OP_time_i, |
6567 | | "time_i", |
6568 | | " ", |
6569 | | 1, |
6570 | | 0, |
6571 | | 0, |
6572 | | 0, |
6573 | | 0, |
6574 | | 0, |
6575 | | 0, |
6576 | | { MVM_operand_write_reg | MVM_operand_int64 } |
6577 | | }, |
6578 | | { |
6579 | | MVM_OP_sleep, |
6580 | | "sleep", |
6581 | | " ", |
6582 | | 1, |
6583 | | 0, |
6584 | | 0, |
6585 | | 0, |
6586 | | 0, |
6587 | | 0, |
6588 | | 0, |
6589 | | { MVM_operand_read_reg | MVM_operand_num64 } |
6590 | | }, |
6591 | | { |
6592 | | MVM_OP_newthread, |
6593 | | "newthread", |
6594 | | " ", |
6595 | | 3, |
6596 | | 0, |
6597 | | 0, |
6598 | | 0, |
6599 | | 0, |
6600 | | 0, |
6601 | | 0, |
6602 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6603 | | }, |
6604 | | { |
6605 | | MVM_OP_threadjoin, |
6606 | | "threadjoin", |
6607 | | " ", |
6608 | | 1, |
6609 | | 0, |
6610 | | 0, |
6611 | | 0, |
6612 | | 0, |
6613 | | 0, |
6614 | | 0, |
6615 | | { MVM_operand_read_reg | MVM_operand_obj } |
6616 | | }, |
6617 | | { |
6618 | | MVM_OP_time_n, |
6619 | | "time_n", |
6620 | | " ", |
6621 | | 1, |
6622 | | 0, |
6623 | | 0, |
6624 | | 0, |
6625 | | 0, |
6626 | | 0, |
6627 | | 0, |
6628 | | { MVM_operand_write_reg | MVM_operand_num64 } |
6629 | | }, |
6630 | | { |
6631 | | MVM_OP_exit, |
6632 | | "exit", |
6633 | | " ", |
6634 | | 1, |
6635 | | 0, |
6636 | | 0, |
6637 | | 0, |
6638 | | 0, |
6639 | | 0, |
6640 | | 0, |
6641 | | { MVM_operand_read_reg | MVM_operand_int64 } |
6642 | | }, |
6643 | | { |
6644 | | MVM_OP_DEPRECATED_30, |
6645 | | "DEPRECATED_30", |
6646 | | " ", |
6647 | | 8, |
6648 | | 0, |
6649 | | 0, |
6650 | | 0, |
6651 | | 0, |
6652 | | 0, |
6653 | | 0, |
6654 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6655 | | }, |
6656 | | { |
6657 | | MVM_OP_cwd, |
6658 | | "cwd", |
6659 | | " ", |
6660 | | 1, |
6661 | | 0, |
6662 | | 0, |
6663 | | 0, |
6664 | | 0, |
6665 | | 0, |
6666 | | 0, |
6667 | | { MVM_operand_write_reg | MVM_operand_str } |
6668 | | }, |
6669 | | { |
6670 | | MVM_OP_clargs, |
6671 | | "clargs", |
6672 | | " ", |
6673 | | 1, |
6674 | | 0, |
6675 | | 0, |
6676 | | 0, |
6677 | | 0, |
6678 | | 0, |
6679 | | 1, |
6680 | | { MVM_operand_write_reg | MVM_operand_obj } |
6681 | | }, |
6682 | | { |
6683 | | MVM_OP_getenvhash, |
6684 | | "getenvhash", |
6685 | | " ", |
6686 | | 1, |
6687 | | 0, |
6688 | | 0, |
6689 | | 0, |
6690 | | 0, |
6691 | | 0, |
6692 | | 1, |
6693 | | { MVM_operand_write_reg | MVM_operand_obj } |
6694 | | }, |
6695 | | { |
6696 | | MVM_OP_loadlib, |
6697 | | "loadlib", |
6698 | | " ", |
6699 | | 2, |
6700 | | 0, |
6701 | | 0, |
6702 | | 0, |
6703 | | 0, |
6704 | | 0, |
6705 | | 0, |
6706 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6707 | | }, |
6708 | | { |
6709 | | MVM_OP_freelib, |
6710 | | "freelib", |
6711 | | " ", |
6712 | | 1, |
6713 | | 0, |
6714 | | 0, |
6715 | | 0, |
6716 | | 0, |
6717 | | 0, |
6718 | | 0, |
6719 | | { MVM_operand_read_reg | MVM_operand_str } |
6720 | | }, |
6721 | | { |
6722 | | MVM_OP_findsym, |
6723 | | "findsym", |
6724 | | " ", |
6725 | | 3, |
6726 | | 0, |
6727 | | 0, |
6728 | | 0, |
6729 | | 0, |
6730 | | 0, |
6731 | | 0, |
6732 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6733 | | }, |
6734 | | { |
6735 | | MVM_OP_dropsym, |
6736 | | "dropsym", |
6737 | | " ", |
6738 | | 1, |
6739 | | 0, |
6740 | | 0, |
6741 | | 0, |
6742 | | 0, |
6743 | | 0, |
6744 | | 0, |
6745 | | { MVM_operand_read_reg | MVM_operand_obj } |
6746 | | }, |
6747 | | { |
6748 | | MVM_OP_loadext, |
6749 | | "loadext", |
6750 | | " ", |
6751 | | 2, |
6752 | | 0, |
6753 | | 0, |
6754 | | 0, |
6755 | | 0, |
6756 | | 0, |
6757 | | 0, |
6758 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6759 | | }, |
6760 | | { |
6761 | | MVM_OP_backendconfig, |
6762 | | "backendconfig", |
6763 | | " ", |
6764 | | 1, |
6765 | | 0, |
6766 | | 0, |
6767 | | 0, |
6768 | | 0, |
6769 | | 0, |
6770 | | 0, |
6771 | | { MVM_operand_write_reg | MVM_operand_obj } |
6772 | | }, |
6773 | | { |
6774 | | MVM_OP_getlexouter, |
6775 | | "getlexouter", |
6776 | | " ", |
6777 | | 2, |
6778 | | 1, |
6779 | | 0, |
6780 | | 0, |
6781 | | 1, |
6782 | | 0, |
6783 | | 1, |
6784 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6785 | | }, |
6786 | | { |
6787 | | MVM_OP_getlexrel, |
6788 | | "getlexrel", |
6789 | | " ", |
6790 | | 3, |
6791 | | 1, |
6792 | | 0, |
6793 | | 0, |
6794 | | 0, |
6795 | | 0, |
6796 | | 1, |
6797 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6798 | | }, |
6799 | | { |
6800 | | MVM_OP_getlexreldyn, |
6801 | | "getlexreldyn", |
6802 | | " ", |
6803 | | 3, |
6804 | | 1, |
6805 | | 0, |
6806 | | 0, |
6807 | | 0, |
6808 | | 0, |
6809 | | 1, |
6810 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6811 | | }, |
6812 | | { |
6813 | | MVM_OP_getlexrelcaller, |
6814 | | "getlexrelcaller", |
6815 | | " ", |
6816 | | 3, |
6817 | | 1, |
6818 | | 0, |
6819 | | 0, |
6820 | | 0, |
6821 | | 0, |
6822 | | 1, |
6823 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6824 | | }, |
6825 | | { |
6826 | | MVM_OP_getlexcaller, |
6827 | | "getlexcaller", |
6828 | | " ", |
6829 | | 2, |
6830 | | 1, |
6831 | | 0, |
6832 | | 0, |
6833 | | 1, |
6834 | | 0, |
6835 | | 1, |
6836 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
6837 | | }, |
6838 | | { |
6839 | | MVM_OP_bitand_s, |
6840 | | "bitand_s", |
6841 | | " ", |
6842 | | 3, |
6843 | | 1, |
6844 | | 0, |
6845 | | 0, |
6846 | | 0, |
6847 | | 0, |
6848 | | 0, |
6849 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6850 | | }, |
6851 | | { |
6852 | | MVM_OP_bitor_s, |
6853 | | "bitor_s", |
6854 | | " ", |
6855 | | 3, |
6856 | | 1, |
6857 | | 0, |
6858 | | 0, |
6859 | | 0, |
6860 | | 0, |
6861 | | 0, |
6862 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6863 | | }, |
6864 | | { |
6865 | | MVM_OP_bitxor_s, |
6866 | | "bitxor_s", |
6867 | | " ", |
6868 | | 3, |
6869 | | 1, |
6870 | | 0, |
6871 | | 0, |
6872 | | 0, |
6873 | | 0, |
6874 | | 0, |
6875 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
6876 | | }, |
6877 | | { |
6878 | | MVM_OP_isnanorinf, |
6879 | | "isnanorinf", |
6880 | | " ", |
6881 | | 2, |
6882 | | 1, |
6883 | | 0, |
6884 | | 0, |
6885 | | 0, |
6886 | | 0, |
6887 | | 0, |
6888 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64 } |
6889 | | }, |
6890 | | { |
6891 | | MVM_OP_inf, |
6892 | | "inf", |
6893 | | " ", |
6894 | | 1, |
6895 | | 1, |
6896 | | 0, |
6897 | | 0, |
6898 | | 0, |
6899 | | 0, |
6900 | | 0, |
6901 | | { MVM_operand_write_reg | MVM_operand_num64 } |
6902 | | }, |
6903 | | { |
6904 | | MVM_OP_neginf, |
6905 | | "neginf", |
6906 | | " ", |
6907 | | 1, |
6908 | | 1, |
6909 | | 0, |
6910 | | 0, |
6911 | | 0, |
6912 | | 0, |
6913 | | 0, |
6914 | | { MVM_operand_write_reg | MVM_operand_num64 } |
6915 | | }, |
6916 | | { |
6917 | | MVM_OP_nan, |
6918 | | "nan", |
6919 | | " ", |
6920 | | 1, |
6921 | | 1, |
6922 | | 0, |
6923 | | 0, |
6924 | | 0, |
6925 | | 0, |
6926 | | 0, |
6927 | | { MVM_operand_write_reg | MVM_operand_num64 } |
6928 | | }, |
6929 | | { |
6930 | | MVM_OP_getpid, |
6931 | | "getpid", |
6932 | | " ", |
6933 | | 1, |
6934 | | 1, |
6935 | | 0, |
6936 | | 0, |
6937 | | 0, |
6938 | | 0, |
6939 | | 0, |
6940 | | { MVM_operand_write_reg | MVM_operand_int64 } |
6941 | | }, |
6942 | | { |
6943 | | MVM_OP_DEPRECATED_29, |
6944 | | "DEPRECATED_29", |
6945 | | " ", |
6946 | | 8, |
6947 | | 0, |
6948 | | 0, |
6949 | | 0, |
6950 | | 0, |
6951 | | 0, |
6952 | | 0, |
6953 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
6954 | | }, |
6955 | | { |
6956 | | MVM_OP_filereadable, |
6957 | | "filereadable", |
6958 | | " ", |
6959 | | 2, |
6960 | | 0, |
6961 | | 0, |
6962 | | 0, |
6963 | | 0, |
6964 | | 0, |
6965 | | 0, |
6966 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
6967 | | }, |
6968 | | { |
6969 | | MVM_OP_filewritable, |
6970 | | "filewritable", |
6971 | | " ", |
6972 | | 2, |
6973 | | 0, |
6974 | | 0, |
6975 | | 0, |
6976 | | 0, |
6977 | | 0, |
6978 | | 0, |
6979 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
6980 | | }, |
6981 | | { |
6982 | | MVM_OP_fileexecutable, |
6983 | | "fileexecutable", |
6984 | | " ", |
6985 | | 2, |
6986 | | 0, |
6987 | | 0, |
6988 | | 0, |
6989 | | 0, |
6990 | | 0, |
6991 | | 0, |
6992 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
6993 | | }, |
6994 | | { |
6995 | | MVM_OP_DEPRECATED_19, |
6996 | | "DEPRECATED_19", |
6997 | | " ", |
6998 | | 3, |
6999 | | 0, |
7000 | | 0, |
7001 | | 0, |
7002 | | 0, |
7003 | | 0, |
7004 | | 0, |
7005 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
7006 | | }, |
7007 | | { |
7008 | | MVM_OP_capturenamedshash, |
7009 | | "capturenamedshash", |
7010 | | " ", |
7011 | | 2, |
7012 | | 1, |
7013 | | 0, |
7014 | | 0, |
7015 | | 0, |
7016 | | 0, |
7017 | | 1, |
7018 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7019 | | }, |
7020 | | { |
7021 | | MVM_OP_read_fhb, |
7022 | | "read_fhb", |
7023 | | " ", |
7024 | | 3, |
7025 | | 0, |
7026 | | 0, |
7027 | | 0, |
7028 | | 0, |
7029 | | 0, |
7030 | | 0, |
7031 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
7032 | | }, |
7033 | | { |
7034 | | MVM_OP_write_fhb, |
7035 | | "write_fhb", |
7036 | | " ", |
7037 | | 2, |
7038 | | 0, |
7039 | | 0, |
7040 | | 0, |
7041 | | 0, |
7042 | | 0, |
7043 | | 0, |
7044 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7045 | | }, |
7046 | | { |
7047 | | MVM_OP_replace, |
7048 | | "replace", |
7049 | | " ", |
7050 | | 5, |
7051 | | 0, |
7052 | | 0, |
7053 | | 0, |
7054 | | 0, |
7055 | | 0, |
7056 | | 0, |
7057 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
7058 | | }, |
7059 | | { |
7060 | | MVM_OP_newexception, |
7061 | | "newexception", |
7062 | | " ", |
7063 | | 1, |
7064 | | 0, |
7065 | | 0, |
7066 | | 0, |
7067 | | 0, |
7068 | | 0, |
7069 | | 0, |
7070 | | { MVM_operand_write_reg | MVM_operand_obj } |
7071 | | }, |
7072 | | { |
7073 | | MVM_OP_permit, |
7074 | | "permit", |
7075 | | " ", |
7076 | | 3, |
7077 | | 0, |
7078 | | 0, |
7079 | | 0, |
7080 | | 0, |
7081 | | 0, |
7082 | | 0, |
7083 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
7084 | | }, |
7085 | | { |
7086 | | MVM_OP_backtrace, |
7087 | | "backtrace", |
7088 | | " ", |
7089 | | 2, |
7090 | | 0, |
7091 | | 0, |
7092 | | 0, |
7093 | | 0, |
7094 | | 0, |
7095 | | 0, |
7096 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7097 | | }, |
7098 | | { |
7099 | | MVM_OP_symlink, |
7100 | | "symlink", |
7101 | | " ", |
7102 | | 2, |
7103 | | 0, |
7104 | | 0, |
7105 | | 0, |
7106 | | 0, |
7107 | | 0, |
7108 | | 0, |
7109 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
7110 | | }, |
7111 | | { |
7112 | | MVM_OP_link, |
7113 | | "link", |
7114 | | " ", |
7115 | | 2, |
7116 | | 0, |
7117 | | 0, |
7118 | | 0, |
7119 | | 0, |
7120 | | 0, |
7121 | | 0, |
7122 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
7123 | | }, |
7124 | | { |
7125 | | MVM_OP_gethostname, |
7126 | | "gethostname", |
7127 | | " ", |
7128 | | 1, |
7129 | | 0, |
7130 | | 0, |
7131 | | 0, |
7132 | | 0, |
7133 | | 0, |
7134 | | 0, |
7135 | | { MVM_operand_write_reg | MVM_operand_str } |
7136 | | }, |
7137 | | { |
7138 | | MVM_OP_exreturnafterunwind, |
7139 | | "exreturnafterunwind", |
7140 | | " ", |
7141 | | 1, |
7142 | | 0, |
7143 | | 0, |
7144 | | 0, |
7145 | | 0, |
7146 | | 0, |
7147 | | 0, |
7148 | | { MVM_operand_read_reg | MVM_operand_obj } |
7149 | | }, |
7150 | | { |
7151 | | MVM_OP_DEPRECATED_13, |
7152 | | "DEPRECATED_13", |
7153 | | " ", |
7154 | | 2, |
7155 | | 0, |
7156 | | 0, |
7157 | | 0, |
7158 | | 0, |
7159 | | 0, |
7160 | | 0, |
7161 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7162 | | }, |
7163 | | { |
7164 | | MVM_OP_continuationreset, |
7165 | | "continuationreset", |
7166 | | " ", |
7167 | | 3, |
7168 | | 0, |
7169 | | 0, |
7170 | | 0, |
7171 | | 0, |
7172 | | 1, |
7173 | | 0, |
7174 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7175 | | }, |
7176 | | { |
7177 | | MVM_OP_continuationcontrol, |
7178 | | "continuationcontrol", |
7179 | | " ", |
7180 | | 4, |
7181 | | 0, |
7182 | | 0, |
7183 | | 0, |
7184 | | 0, |
7185 | | 1, |
7186 | | 0, |
7187 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7188 | | }, |
7189 | | { |
7190 | | MVM_OP_continuationinvoke, |
7191 | | "continuationinvoke", |
7192 | | " ", |
7193 | | 3, |
7194 | | 0, |
7195 | | 0, |
7196 | | 0, |
7197 | | 0, |
7198 | | 1, |
7199 | | 0, |
7200 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7201 | | }, |
7202 | | { |
7203 | | MVM_OP_randscale_n, |
7204 | | "randscale_n", |
7205 | | " ", |
7206 | | 2, |
7207 | | 1, |
7208 | | 0, |
7209 | | 0, |
7210 | | 0, |
7211 | | 0, |
7212 | | 0, |
7213 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_num64 } |
7214 | | }, |
7215 | | { |
7216 | | MVM_OP_uniisblock, |
7217 | | "uniisblock", |
7218 | | " ", |
7219 | | 4, |
7220 | | 1, |
7221 | | 0, |
7222 | | 0, |
7223 | | 0, |
7224 | | 0, |
7225 | | 0, |
7226 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
7227 | | }, |
7228 | | { |
7229 | | MVM_OP_assertparamcheck, |
7230 | | "assertparamcheck", |
7231 | | " ", |
7232 | | 1, |
7233 | | 0, |
7234 | | 0, |
7235 | | 0, |
7236 | | 1, |
7237 | | 1, |
7238 | | 0, |
7239 | | { MVM_operand_read_reg | MVM_operand_int64 } |
7240 | | }, |
7241 | | { |
7242 | | MVM_OP_hintfor, |
7243 | | "hintfor", |
7244 | | " ", |
7245 | | 3, |
7246 | | 0, |
7247 | | 0, |
7248 | | 0, |
7249 | | 0, |
7250 | | 0, |
7251 | | 0, |
7252 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
7253 | | }, |
7254 | | { |
7255 | | MVM_OP_paramnamesused, |
7256 | | "paramnamesused", |
7257 | | " ", |
7258 | | 0, |
7259 | | 0, |
7260 | | 0, |
7261 | | 0, |
7262 | | 1, |
7263 | | 0, |
7264 | | 0, |
7265 | | }, |
7266 | | { |
7267 | | MVM_OP_getuniname, |
7268 | | "getuniname", |
7269 | | " ", |
7270 | | 2, |
7271 | | 0, |
7272 | | 0, |
7273 | | 0, |
7274 | | 0, |
7275 | | 0, |
7276 | | 0, |
7277 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
7278 | | }, |
7279 | | { |
7280 | | MVM_OP_getuniprop_int, |
7281 | | "getuniprop_int", |
7282 | | " ", |
7283 | | 3, |
7284 | | 0, |
7285 | | 0, |
7286 | | 0, |
7287 | | 0, |
7288 | | 0, |
7289 | | 0, |
7290 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
7291 | | }, |
7292 | | { |
7293 | | MVM_OP_getuniprop_bool, |
7294 | | "getuniprop_bool", |
7295 | | " ", |
7296 | | 3, |
7297 | | 0, |
7298 | | 0, |
7299 | | 0, |
7300 | | 0, |
7301 | | 0, |
7302 | | 0, |
7303 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
7304 | | }, |
7305 | | { |
7306 | | MVM_OP_getuniprop_str, |
7307 | | "getuniprop_str", |
7308 | | " ", |
7309 | | 3, |
7310 | | 0, |
7311 | | 0, |
7312 | | 0, |
7313 | | 0, |
7314 | | 0, |
7315 | | 0, |
7316 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
7317 | | }, |
7318 | | { |
7319 | | MVM_OP_matchuniprop, |
7320 | | "matchuniprop", |
7321 | | " ", |
7322 | | 4, |
7323 | | 0, |
7324 | | 0, |
7325 | | 0, |
7326 | | 0, |
7327 | | 0, |
7328 | | 0, |
7329 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
7330 | | }, |
7331 | | { |
7332 | | MVM_OP_nativecallbuild, |
7333 | | "nativecallbuild", |
7334 | | " ", |
7335 | | 7, |
7336 | | 0, |
7337 | | 0, |
7338 | | 0, |
7339 | | 0, |
7340 | | 0, |
7341 | | 0, |
7342 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7343 | | }, |
7344 | | { |
7345 | | MVM_OP_nativecallinvoke, |
7346 | | "nativecallinvoke", |
7347 | | " ", |
7348 | | 4, |
7349 | | 0, |
7350 | | 0, |
7351 | | 0, |
7352 | | 0, |
7353 | | 0, |
7354 | | 0, |
7355 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7356 | | }, |
7357 | | { |
7358 | | MVM_OP_nativecallrefresh, |
7359 | | "nativecallrefresh", |
7360 | | " ", |
7361 | | 1, |
7362 | | 0, |
7363 | | 0, |
7364 | | 0, |
7365 | | 0, |
7366 | | 0, |
7367 | | 0, |
7368 | | { MVM_operand_read_reg | MVM_operand_obj } |
7369 | | }, |
7370 | | { |
7371 | | MVM_OP_threadrun, |
7372 | | "threadrun", |
7373 | | " ", |
7374 | | 1, |
7375 | | 0, |
7376 | | 0, |
7377 | | 0, |
7378 | | 0, |
7379 | | 0, |
7380 | | 0, |
7381 | | { MVM_operand_read_reg | MVM_operand_obj } |
7382 | | }, |
7383 | | { |
7384 | | MVM_OP_threadid, |
7385 | | "threadid", |
7386 | | " ", |
7387 | | 2, |
7388 | | 0, |
7389 | | 0, |
7390 | | 0, |
7391 | | 0, |
7392 | | 0, |
7393 | | 0, |
7394 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7395 | | }, |
7396 | | { |
7397 | | MVM_OP_threadyield, |
7398 | | "threadyield", |
7399 | | " ", |
7400 | | 0, |
7401 | | 0, |
7402 | | 0, |
7403 | | 0, |
7404 | | 0, |
7405 | | 0, |
7406 | | 0, |
7407 | | }, |
7408 | | { |
7409 | | MVM_OP_currentthread, |
7410 | | "currentthread", |
7411 | | " ", |
7412 | | 1, |
7413 | | 0, |
7414 | | 0, |
7415 | | 0, |
7416 | | 0, |
7417 | | 0, |
7418 | | 0, |
7419 | | { MVM_operand_write_reg | MVM_operand_obj } |
7420 | | }, |
7421 | | { |
7422 | | MVM_OP_lock, |
7423 | | "lock", |
7424 | | " ", |
7425 | | 1, |
7426 | | 0, |
7427 | | 0, |
7428 | | 0, |
7429 | | 0, |
7430 | | 0, |
7431 | | 0, |
7432 | | { MVM_operand_read_reg | MVM_operand_obj } |
7433 | | }, |
7434 | | { |
7435 | | MVM_OP_unlock, |
7436 | | "unlock", |
7437 | | " ", |
7438 | | 1, |
7439 | | 0, |
7440 | | 0, |
7441 | | 0, |
7442 | | 0, |
7443 | | 0, |
7444 | | 0, |
7445 | | { MVM_operand_read_reg | MVM_operand_obj } |
7446 | | }, |
7447 | | { |
7448 | | MVM_OP_semacquire, |
7449 | | "semacquire", |
7450 | | " ", |
7451 | | 1, |
7452 | | 0, |
7453 | | 0, |
7454 | | 0, |
7455 | | 0, |
7456 | | 0, |
7457 | | 0, |
7458 | | { MVM_operand_read_reg | MVM_operand_obj } |
7459 | | }, |
7460 | | { |
7461 | | MVM_OP_semtryacquire, |
7462 | | "semtryacquire", |
7463 | | " ", |
7464 | | 2, |
7465 | | 0, |
7466 | | 0, |
7467 | | 0, |
7468 | | 0, |
7469 | | 0, |
7470 | | 0, |
7471 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7472 | | }, |
7473 | | { |
7474 | | MVM_OP_semrelease, |
7475 | | "semrelease", |
7476 | | " ", |
7477 | | 1, |
7478 | | 0, |
7479 | | 0, |
7480 | | 0, |
7481 | | 0, |
7482 | | 0, |
7483 | | 0, |
7484 | | { MVM_operand_read_reg | MVM_operand_obj } |
7485 | | }, |
7486 | | { |
7487 | | MVM_OP_getlockcondvar, |
7488 | | "getlockcondvar", |
7489 | | " ", |
7490 | | 3, |
7491 | | 0, |
7492 | | 0, |
7493 | | 0, |
7494 | | 0, |
7495 | | 0, |
7496 | | 0, |
7497 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7498 | | }, |
7499 | | { |
7500 | | MVM_OP_condwait, |
7501 | | "condwait", |
7502 | | " ", |
7503 | | 1, |
7504 | | 0, |
7505 | | 0, |
7506 | | 0, |
7507 | | 0, |
7508 | | 0, |
7509 | | 0, |
7510 | | { MVM_operand_read_reg | MVM_operand_obj } |
7511 | | }, |
7512 | | { |
7513 | | MVM_OP_condsignalone, |
7514 | | "condsignalone", |
7515 | | " ", |
7516 | | 1, |
7517 | | 0, |
7518 | | 0, |
7519 | | 0, |
7520 | | 0, |
7521 | | 0, |
7522 | | 0, |
7523 | | { MVM_operand_read_reg | MVM_operand_obj } |
7524 | | }, |
7525 | | { |
7526 | | MVM_OP_condsignalall, |
7527 | | "condsignalall", |
7528 | | " ", |
7529 | | 1, |
7530 | | 0, |
7531 | | 0, |
7532 | | 0, |
7533 | | 0, |
7534 | | 0, |
7535 | | 0, |
7536 | | { MVM_operand_read_reg | MVM_operand_obj } |
7537 | | }, |
7538 | | { |
7539 | | MVM_OP_queuepoll, |
7540 | | "queuepoll", |
7541 | | " ", |
7542 | | 2, |
7543 | | 0, |
7544 | | 0, |
7545 | | 0, |
7546 | | 0, |
7547 | | 0, |
7548 | | 0, |
7549 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7550 | | }, |
7551 | | { |
7552 | | MVM_OP_setmultispec, |
7553 | | "setmultispec", |
7554 | | " ", |
7555 | | 4, |
7556 | | 0, |
7557 | | 0, |
7558 | | 0, |
7559 | | 0, |
7560 | | 0, |
7561 | | 0, |
7562 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
7563 | | }, |
7564 | | { |
7565 | | MVM_OP_ctxouterskipthunks, |
7566 | | "ctxouterskipthunks", |
7567 | | " ", |
7568 | | 2, |
7569 | | 0, |
7570 | | 0, |
7571 | | 0, |
7572 | | 1, |
7573 | | 0, |
7574 | | 0, |
7575 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7576 | | }, |
7577 | | { |
7578 | | MVM_OP_ctxcallerskipthunks, |
7579 | | "ctxcallerskipthunks", |
7580 | | " ", |
7581 | | 2, |
7582 | | 0, |
7583 | | 0, |
7584 | | 0, |
7585 | | 1, |
7586 | | 0, |
7587 | | 0, |
7588 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7589 | | }, |
7590 | | { |
7591 | | MVM_OP_timer, |
7592 | | "timer", |
7593 | | " ", |
7594 | | 6, |
7595 | | 0, |
7596 | | 0, |
7597 | | 0, |
7598 | | 0, |
7599 | | 0, |
7600 | | 0, |
7601 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7602 | | }, |
7603 | | { |
7604 | | MVM_OP_cancel, |
7605 | | "cancel", |
7606 | | " ", |
7607 | | 1, |
7608 | | 0, |
7609 | | 0, |
7610 | | 0, |
7611 | | 0, |
7612 | | 0, |
7613 | | 0, |
7614 | | { MVM_operand_read_reg | MVM_operand_obj } |
7615 | | }, |
7616 | | { |
7617 | | MVM_OP_signal, |
7618 | | "signal", |
7619 | | " ", |
7620 | | 5, |
7621 | | 0, |
7622 | | 0, |
7623 | | 0, |
7624 | | 0, |
7625 | | 0, |
7626 | | 0, |
7627 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7628 | | }, |
7629 | | { |
7630 | | MVM_OP_watchfile, |
7631 | | "watchfile", |
7632 | | " ", |
7633 | | 5, |
7634 | | 0, |
7635 | | 0, |
7636 | | 0, |
7637 | | 0, |
7638 | | 0, |
7639 | | 0, |
7640 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
7641 | | }, |
7642 | | { |
7643 | | MVM_OP_asyncconnect, |
7644 | | "asyncconnect", |
7645 | | " ", |
7646 | | 6, |
7647 | | 0, |
7648 | | 0, |
7649 | | 0, |
7650 | | 0, |
7651 | | 0, |
7652 | | 0, |
7653 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7654 | | }, |
7655 | | { |
7656 | | MVM_OP_asynclisten, |
7657 | | "asynclisten", |
7658 | | " ", |
7659 | | 7, |
7660 | | 0, |
7661 | | 0, |
7662 | | 0, |
7663 | | 0, |
7664 | | 0, |
7665 | | 0, |
7666 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7667 | | }, |
7668 | | { |
7669 | | MVM_OP_DEPRECATED_14, |
7670 | | "DEPRECATED_14", |
7671 | | " ", |
7672 | | 6, |
7673 | | 0, |
7674 | | 0, |
7675 | | 0, |
7676 | | 0, |
7677 | | 0, |
7678 | | 0, |
7679 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
7680 | | }, |
7681 | | { |
7682 | | MVM_OP_asyncwritebytes, |
7683 | | "asyncwritebytes", |
7684 | | " ", |
7685 | | 6, |
7686 | | 0, |
7687 | | 0, |
7688 | | 0, |
7689 | | 0, |
7690 | | 0, |
7691 | | 0, |
7692 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7693 | | }, |
7694 | | { |
7695 | | MVM_OP_DEPRECATED_16, |
7696 | | "DEPRECATED_16", |
7697 | | " ", |
7698 | | 5, |
7699 | | 0, |
7700 | | 0, |
7701 | | 0, |
7702 | | 0, |
7703 | | 0, |
7704 | | 0, |
7705 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7706 | | }, |
7707 | | { |
7708 | | MVM_OP_asyncreadbytes, |
7709 | | "asyncreadbytes", |
7710 | | " ", |
7711 | | 6, |
7712 | | 0, |
7713 | | 0, |
7714 | | 0, |
7715 | | 0, |
7716 | | 0, |
7717 | | 0, |
7718 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7719 | | }, |
7720 | | { |
7721 | | MVM_OP_getlexstatic_o, |
7722 | | "getlexstatic_o", |
7723 | | " ", |
7724 | | 2, |
7725 | | 1, |
7726 | | 0, |
7727 | | 1, |
7728 | | 1, |
7729 | | 0, |
7730 | | 0, |
7731 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
7732 | | }, |
7733 | | { |
7734 | | MVM_OP_getlexperinvtype_o, |
7735 | | "getlexperinvtype_o", |
7736 | | " ", |
7737 | | 2, |
7738 | | 1, |
7739 | | 0, |
7740 | | 1, |
7741 | | 1, |
7742 | | 0, |
7743 | | 0, |
7744 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
7745 | | }, |
7746 | | { |
7747 | | MVM_OP_execname, |
7748 | | "execname", |
7749 | | " ", |
7750 | | 1, |
7751 | | 0, |
7752 | | 0, |
7753 | | 0, |
7754 | | 0, |
7755 | | 0, |
7756 | | 0, |
7757 | | { MVM_operand_write_reg | MVM_operand_str } |
7758 | | }, |
7759 | | { |
7760 | | MVM_OP_const_i64_16, |
7761 | | "const_i64_16", |
7762 | | " ", |
7763 | | 2, |
7764 | | 1, |
7765 | | 0, |
7766 | | 0, |
7767 | | 0, |
7768 | | 0, |
7769 | | 0, |
7770 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_int16 } |
7771 | | }, |
7772 | | { |
7773 | | MVM_OP_const_i64_32, |
7774 | | "const_i64_32", |
7775 | | " ", |
7776 | | 2, |
7777 | | 1, |
7778 | | 0, |
7779 | | 0, |
7780 | | 0, |
7781 | | 0, |
7782 | | 0, |
7783 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_int32 } |
7784 | | }, |
7785 | | { |
7786 | | MVM_OP_isnonnull, |
7787 | | "isnonnull", |
7788 | | " ", |
7789 | | 2, |
7790 | | 1, |
7791 | | 0, |
7792 | | 0, |
7793 | | 0, |
7794 | | 0, |
7795 | | 0, |
7796 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7797 | | }, |
7798 | | { |
7799 | | MVM_OP_param_rn2_i, |
7800 | | "param_rn2_i", |
7801 | | " ", |
7802 | | 3, |
7803 | | 0, |
7804 | | 0, |
7805 | | 0, |
7806 | | 1, |
7807 | | 0, |
7808 | | 0, |
7809 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_str, MVM_operand_str } |
7810 | | }, |
7811 | | { |
7812 | | MVM_OP_param_rn2_n, |
7813 | | "param_rn2_n", |
7814 | | " ", |
7815 | | 3, |
7816 | | 0, |
7817 | | 0, |
7818 | | 0, |
7819 | | 1, |
7820 | | 0, |
7821 | | 0, |
7822 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_str, MVM_operand_str } |
7823 | | }, |
7824 | | { |
7825 | | MVM_OP_param_rn2_s, |
7826 | | "param_rn2_s", |
7827 | | " ", |
7828 | | 3, |
7829 | | 0, |
7830 | | 0, |
7831 | | 0, |
7832 | | 1, |
7833 | | 0, |
7834 | | 0, |
7835 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_str, MVM_operand_str } |
7836 | | }, |
7837 | | { |
7838 | | MVM_OP_param_rn2_o, |
7839 | | "param_rn2_o", |
7840 | | " ", |
7841 | | 3, |
7842 | | 0, |
7843 | | 0, |
7844 | | 0, |
7845 | | 1, |
7846 | | 0, |
7847 | | 1, |
7848 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_str } |
7849 | | }, |
7850 | | { |
7851 | | MVM_OP_param_on2_i, |
7852 | | "param_on2_i", |
7853 | | " ", |
7854 | | 4, |
7855 | | 0, |
7856 | | 0, |
7857 | | 0, |
7858 | | 1, |
7859 | | 0, |
7860 | | 0, |
7861 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_str, MVM_operand_str, MVM_operand_ins } |
7862 | | }, |
7863 | | { |
7864 | | MVM_OP_param_on2_n, |
7865 | | "param_on2_n", |
7866 | | " ", |
7867 | | 4, |
7868 | | 0, |
7869 | | 0, |
7870 | | 0, |
7871 | | 1, |
7872 | | 0, |
7873 | | 0, |
7874 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_str, MVM_operand_str, MVM_operand_ins } |
7875 | | }, |
7876 | | { |
7877 | | MVM_OP_param_on2_s, |
7878 | | "param_on2_s", |
7879 | | " ", |
7880 | | 4, |
7881 | | 0, |
7882 | | 0, |
7883 | | 0, |
7884 | | 1, |
7885 | | 0, |
7886 | | 0, |
7887 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_str, MVM_operand_str, MVM_operand_ins } |
7888 | | }, |
7889 | | { |
7890 | | MVM_OP_param_on2_o, |
7891 | | "param_on2_o", |
7892 | | " ", |
7893 | | 4, |
7894 | | 0, |
7895 | | 0, |
7896 | | 0, |
7897 | | 1, |
7898 | | 0, |
7899 | | 1, |
7900 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_str, MVM_operand_ins } |
7901 | | }, |
7902 | | { |
7903 | | MVM_OP_osrpoint, |
7904 | | "osrpoint", |
7905 | | " ", |
7906 | | 0, |
7907 | | 0, |
7908 | | 4, |
7909 | | 0, |
7910 | | 0, |
7911 | | 0, |
7912 | | 0, |
7913 | | }, |
7914 | | { |
7915 | | MVM_OP_nativecallcast, |
7916 | | "nativecallcast", |
7917 | | " ", |
7918 | | 4, |
7919 | | 0, |
7920 | | 0, |
7921 | | 0, |
7922 | | 0, |
7923 | | 0, |
7924 | | 0, |
7925 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7926 | | }, |
7927 | | { |
7928 | | MVM_OP_spawnprocasync, |
7929 | | "spawnprocasync", |
7930 | | " ", |
7931 | | 6, |
7932 | | 0, |
7933 | | 0, |
7934 | | 0, |
7935 | | 0, |
7936 | | 0, |
7937 | | 0, |
7938 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
7939 | | }, |
7940 | | { |
7941 | | MVM_OP_killprocasync, |
7942 | | "killprocasync", |
7943 | | " ", |
7944 | | 2, |
7945 | | 0, |
7946 | | 0, |
7947 | | 0, |
7948 | | 0, |
7949 | | 0, |
7950 | | 0, |
7951 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
7952 | | }, |
7953 | | { |
7954 | | MVM_OP_startprofile, |
7955 | | "startprofile", |
7956 | | " ", |
7957 | | 1, |
7958 | | 0, |
7959 | | 0, |
7960 | | 0, |
7961 | | 0, |
7962 | | 0, |
7963 | | 0, |
7964 | | { MVM_operand_read_reg | MVM_operand_obj } |
7965 | | }, |
7966 | | { |
7967 | | MVM_OP_endprofile, |
7968 | | "endprofile", |
7969 | | " ", |
7970 | | 1, |
7971 | | 0, |
7972 | | 0, |
7973 | | 0, |
7974 | | 0, |
7975 | | 0, |
7976 | | 0, |
7977 | | { MVM_operand_write_reg | MVM_operand_obj } |
7978 | | }, |
7979 | | { |
7980 | | MVM_OP_objectid, |
7981 | | "objectid", |
7982 | | " ", |
7983 | | 2, |
7984 | | 0, |
7985 | | 0, |
7986 | | 0, |
7987 | | 0, |
7988 | | 0, |
7989 | | 0, |
7990 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
7991 | | }, |
7992 | | { |
7993 | | MVM_OP_settypefinalize, |
7994 | | "settypefinalize", |
7995 | | " ", |
7996 | | 2, |
7997 | | 0, |
7998 | | 0, |
7999 | | 0, |
8000 | | 0, |
8001 | | 0, |
8002 | | 0, |
8003 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8004 | | }, |
8005 | | { |
8006 | | MVM_OP_force_gc, |
8007 | | "force_gc", |
8008 | | " ", |
8009 | | 0, |
8010 | | 0, |
8011 | | 0, |
8012 | | 0, |
8013 | | 0, |
8014 | | 0, |
8015 | | 0, |
8016 | | }, |
8017 | | { |
8018 | | MVM_OP_nativecallglobal, |
8019 | | "nativecallglobal", |
8020 | | " ", |
8021 | | 5, |
8022 | | 0, |
8023 | | 0, |
8024 | | 0, |
8025 | | 0, |
8026 | | 0, |
8027 | | 0, |
8028 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8029 | | }, |
8030 | | { |
8031 | | MVM_OP_DEPRECATED_32, |
8032 | | "DEPRECATED_32", |
8033 | | " ", |
8034 | | 2, |
8035 | | 0, |
8036 | | 0, |
8037 | | 0, |
8038 | | 0, |
8039 | | 0, |
8040 | | 0, |
8041 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8042 | | }, |
8043 | | { |
8044 | | MVM_OP_setparameterizer, |
8045 | | "setparameterizer", |
8046 | | " ", |
8047 | | 2, |
8048 | | 0, |
8049 | | 0, |
8050 | | 0, |
8051 | | 0, |
8052 | | 0, |
8053 | | 0, |
8054 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8055 | | }, |
8056 | | { |
8057 | | MVM_OP_parameterizetype, |
8058 | | "parameterizetype", |
8059 | | " ", |
8060 | | 3, |
8061 | | 0, |
8062 | | 0, |
8063 | | 0, |
8064 | | 0, |
8065 | | 1, |
8066 | | 0, |
8067 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8068 | | }, |
8069 | | { |
8070 | | MVM_OP_typeparameterized, |
8071 | | "typeparameterized", |
8072 | | " ", |
8073 | | 2, |
8074 | | 0, |
8075 | | 0, |
8076 | | 0, |
8077 | | 0, |
8078 | | 0, |
8079 | | 0, |
8080 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8081 | | }, |
8082 | | { |
8083 | | MVM_OP_typeparameters, |
8084 | | "typeparameters", |
8085 | | " ", |
8086 | | 2, |
8087 | | 0, |
8088 | | 0, |
8089 | | 0, |
8090 | | 0, |
8091 | | 0, |
8092 | | 0, |
8093 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8094 | | }, |
8095 | | { |
8096 | | MVM_OP_typeparameterat, |
8097 | | "typeparameterat", |
8098 | | " ", |
8099 | | 3, |
8100 | | 0, |
8101 | | 0, |
8102 | | 0, |
8103 | | 0, |
8104 | | 0, |
8105 | | 0, |
8106 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8107 | | }, |
8108 | | { |
8109 | | MVM_OP_readlink, |
8110 | | "readlink", |
8111 | | " ", |
8112 | | 2, |
8113 | | 0, |
8114 | | 0, |
8115 | | 0, |
8116 | | 0, |
8117 | | 0, |
8118 | | 0, |
8119 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
8120 | | }, |
8121 | | { |
8122 | | MVM_OP_lstat, |
8123 | | "lstat", |
8124 | | " ", |
8125 | | 3, |
8126 | | 0, |
8127 | | 0, |
8128 | | 0, |
8129 | | 0, |
8130 | | 0, |
8131 | | 0, |
8132 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
8133 | | }, |
8134 | | { |
8135 | | MVM_OP_iscont_i, |
8136 | | "iscont_i", |
8137 | | " ", |
8138 | | 2, |
8139 | | 1, |
8140 | | 0, |
8141 | | 0, |
8142 | | 0, |
8143 | | 0, |
8144 | | 0, |
8145 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8146 | | }, |
8147 | | { |
8148 | | MVM_OP_iscont_n, |
8149 | | "iscont_n", |
8150 | | " ", |
8151 | | 2, |
8152 | | 1, |
8153 | | 0, |
8154 | | 0, |
8155 | | 0, |
8156 | | 0, |
8157 | | 0, |
8158 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8159 | | }, |
8160 | | { |
8161 | | MVM_OP_iscont_s, |
8162 | | "iscont_s", |
8163 | | " ", |
8164 | | 2, |
8165 | | 1, |
8166 | | 0, |
8167 | | 0, |
8168 | | 0, |
8169 | | 0, |
8170 | | 0, |
8171 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8172 | | }, |
8173 | | { |
8174 | | MVM_OP_assign_i, |
8175 | | "assign_i", |
8176 | | " ", |
8177 | | 2, |
8178 | | 0, |
8179 | | 0, |
8180 | | 0, |
8181 | | 0, |
8182 | | 1, |
8183 | | 0, |
8184 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8185 | | }, |
8186 | | { |
8187 | | MVM_OP_assign_n, |
8188 | | "assign_n", |
8189 | | " ", |
8190 | | 2, |
8191 | | 0, |
8192 | | 0, |
8193 | | 0, |
8194 | | 0, |
8195 | | 1, |
8196 | | 0, |
8197 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64 } |
8198 | | }, |
8199 | | { |
8200 | | MVM_OP_assign_s, |
8201 | | "assign_s", |
8202 | | " ", |
8203 | | 2, |
8204 | | 0, |
8205 | | 0, |
8206 | | 0, |
8207 | | 0, |
8208 | | 1, |
8209 | | 0, |
8210 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
8211 | | }, |
8212 | | { |
8213 | | MVM_OP_decont_i, |
8214 | | "decont_i", |
8215 | | " ", |
8216 | | 2, |
8217 | | 1, |
8218 | | 0, |
8219 | | 0, |
8220 | | 0, |
8221 | | 1, |
8222 | | 0, |
8223 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8224 | | }, |
8225 | | { |
8226 | | MVM_OP_decont_n, |
8227 | | "decont_n", |
8228 | | " ", |
8229 | | 2, |
8230 | | 1, |
8231 | | 0, |
8232 | | 0, |
8233 | | 0, |
8234 | | 1, |
8235 | | 0, |
8236 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj } |
8237 | | }, |
8238 | | { |
8239 | | MVM_OP_decont_s, |
8240 | | "decont_s", |
8241 | | " ", |
8242 | | 2, |
8243 | | 1, |
8244 | | 0, |
8245 | | 0, |
8246 | | 0, |
8247 | | 1, |
8248 | | 0, |
8249 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
8250 | | }, |
8251 | | { |
8252 | | MVM_OP_getrusage, |
8253 | | "getrusage", |
8254 | | " ", |
8255 | | 1, |
8256 | | 1, |
8257 | | 0, |
8258 | | 0, |
8259 | | 0, |
8260 | | 0, |
8261 | | 0, |
8262 | | { MVM_operand_read_reg | MVM_operand_obj } |
8263 | | }, |
8264 | | { |
8265 | | MVM_OP_threadlockcount, |
8266 | | "threadlockcount", |
8267 | | " ", |
8268 | | 2, |
8269 | | 0, |
8270 | | 0, |
8271 | | 0, |
8272 | | 0, |
8273 | | 0, |
8274 | | 0, |
8275 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8276 | | }, |
8277 | | { |
8278 | | MVM_OP_DEPRECATED_4, |
8279 | | "DEPRECATED_4", |
8280 | | " ", |
8281 | | 2, |
8282 | | 1, |
8283 | | 0, |
8284 | | 0, |
8285 | | 1, |
8286 | | 0, |
8287 | | 0, |
8288 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
8289 | | }, |
8290 | | { |
8291 | | MVM_OP_getlexref_i, |
8292 | | "getlexref_i", |
8293 | | " ", |
8294 | | 2, |
8295 | | 1, |
8296 | | 0, |
8297 | | 0, |
8298 | | 1, |
8299 | | 0, |
8300 | | 0, |
8301 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_int64 } |
8302 | | }, |
8303 | | { |
8304 | | MVM_OP_getlexref_n, |
8305 | | "getlexref_n", |
8306 | | " ", |
8307 | | 2, |
8308 | | 1, |
8309 | | 0, |
8310 | | 0, |
8311 | | 1, |
8312 | | 0, |
8313 | | 0, |
8314 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_num64 } |
8315 | | }, |
8316 | | { |
8317 | | MVM_OP_getlexref_s, |
8318 | | "getlexref_s", |
8319 | | " ", |
8320 | | 2, |
8321 | | 1, |
8322 | | 0, |
8323 | | 0, |
8324 | | 1, |
8325 | | 0, |
8326 | | 0, |
8327 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_str } |
8328 | | }, |
8329 | | { |
8330 | | MVM_OP_getlexref_ni, |
8331 | | "getlexref_ni", |
8332 | | " ", |
8333 | | 2, |
8334 | | 1, |
8335 | | 0, |
8336 | | 0, |
8337 | | 1, |
8338 | | 0, |
8339 | | 0, |
8340 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
8341 | | }, |
8342 | | { |
8343 | | MVM_OP_getlexref_nn, |
8344 | | "getlexref_nn", |
8345 | | " ", |
8346 | | 2, |
8347 | | 1, |
8348 | | 0, |
8349 | | 0, |
8350 | | 1, |
8351 | | 0, |
8352 | | 0, |
8353 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
8354 | | }, |
8355 | | { |
8356 | | MVM_OP_getlexref_ns, |
8357 | | "getlexref_ns", |
8358 | | " ", |
8359 | | 2, |
8360 | | 1, |
8361 | | 0, |
8362 | | 0, |
8363 | | 1, |
8364 | | 0, |
8365 | | 0, |
8366 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
8367 | | }, |
8368 | | { |
8369 | | MVM_OP_atposref_i, |
8370 | | "atposref_i", |
8371 | | " ", |
8372 | | 3, |
8373 | | 1, |
8374 | | 0, |
8375 | | 0, |
8376 | | 0, |
8377 | | 0, |
8378 | | 0, |
8379 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8380 | | }, |
8381 | | { |
8382 | | MVM_OP_atposref_n, |
8383 | | "atposref_n", |
8384 | | " ", |
8385 | | 3, |
8386 | | 1, |
8387 | | 0, |
8388 | | 0, |
8389 | | 0, |
8390 | | 0, |
8391 | | 0, |
8392 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8393 | | }, |
8394 | | { |
8395 | | MVM_OP_atposref_s, |
8396 | | "atposref_s", |
8397 | | " ", |
8398 | | 3, |
8399 | | 1, |
8400 | | 0, |
8401 | | 0, |
8402 | | 0, |
8403 | | 0, |
8404 | | 0, |
8405 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8406 | | }, |
8407 | | { |
8408 | | MVM_OP_getattrref_i, |
8409 | | "getattrref_i", |
8410 | | " ", |
8411 | | 5, |
8412 | | 1, |
8413 | | 0, |
8414 | | 0, |
8415 | | 0, |
8416 | | 0, |
8417 | | 0, |
8418 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
8419 | | }, |
8420 | | { |
8421 | | MVM_OP_getattrref_n, |
8422 | | "getattrref_n", |
8423 | | " ", |
8424 | | 5, |
8425 | | 1, |
8426 | | 0, |
8427 | | 0, |
8428 | | 0, |
8429 | | 0, |
8430 | | 0, |
8431 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
8432 | | }, |
8433 | | { |
8434 | | MVM_OP_getattrref_s, |
8435 | | "getattrref_s", |
8436 | | " ", |
8437 | | 5, |
8438 | | 1, |
8439 | | 0, |
8440 | | 0, |
8441 | | 0, |
8442 | | 0, |
8443 | | 0, |
8444 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_int16 } |
8445 | | }, |
8446 | | { |
8447 | | MVM_OP_getattrsref_i, |
8448 | | "getattrsref_i", |
8449 | | " ", |
8450 | | 4, |
8451 | | 1, |
8452 | | 0, |
8453 | | 0, |
8454 | | 0, |
8455 | | 0, |
8456 | | 0, |
8457 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
8458 | | }, |
8459 | | { |
8460 | | MVM_OP_getattrsref_n, |
8461 | | "getattrsref_n", |
8462 | | " ", |
8463 | | 4, |
8464 | | 1, |
8465 | | 0, |
8466 | | 0, |
8467 | | 0, |
8468 | | 0, |
8469 | | 0, |
8470 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
8471 | | }, |
8472 | | { |
8473 | | MVM_OP_getattrsref_s, |
8474 | | "getattrsref_s", |
8475 | | " ", |
8476 | | 4, |
8477 | | 1, |
8478 | | 0, |
8479 | | 0, |
8480 | | 0, |
8481 | | 0, |
8482 | | 0, |
8483 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
8484 | | }, |
8485 | | { |
8486 | | MVM_OP_nativecallsizeof, |
8487 | | "nativecallsizeof", |
8488 | | " ", |
8489 | | 2, |
8490 | | 0, |
8491 | | 0, |
8492 | | 0, |
8493 | | 0, |
8494 | | 0, |
8495 | | 0, |
8496 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8497 | | }, |
8498 | | { |
8499 | | MVM_OP_encodenorm, |
8500 | | "encodenorm", |
8501 | | " ", |
8502 | | 4, |
8503 | | 0, |
8504 | | 0, |
8505 | | 0, |
8506 | | 0, |
8507 | | 0, |
8508 | | 0, |
8509 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8510 | | }, |
8511 | | { |
8512 | | MVM_OP_normalizecodes, |
8513 | | "normalizecodes", |
8514 | | " ", |
8515 | | 3, |
8516 | | 0, |
8517 | | 0, |
8518 | | 0, |
8519 | | 0, |
8520 | | 0, |
8521 | | 0, |
8522 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8523 | | }, |
8524 | | { |
8525 | | MVM_OP_strfromcodes, |
8526 | | "strfromcodes", |
8527 | | " ", |
8528 | | 2, |
8529 | | 0, |
8530 | | 0, |
8531 | | 0, |
8532 | | 0, |
8533 | | 0, |
8534 | | 0, |
8535 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
8536 | | }, |
8537 | | { |
8538 | | MVM_OP_strtocodes, |
8539 | | "strtocodes", |
8540 | | " ", |
8541 | | 3, |
8542 | | 0, |
8543 | | 0, |
8544 | | 0, |
8545 | | 0, |
8546 | | 0, |
8547 | | 0, |
8548 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8549 | | }, |
8550 | | { |
8551 | | MVM_OP_getcodelocation, |
8552 | | "getcodelocation", |
8553 | | " ", |
8554 | | 2, |
8555 | | 1, |
8556 | | 0, |
8557 | | 0, |
8558 | | 0, |
8559 | | 0, |
8560 | | 0, |
8561 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8562 | | }, |
8563 | | { |
8564 | | MVM_OP_eqatim_s, |
8565 | | "eqatim_s", |
8566 | | " ", |
8567 | | 4, |
8568 | | 1, |
8569 | | 0, |
8570 | | 0, |
8571 | | 0, |
8572 | | 0, |
8573 | | 0, |
8574 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
8575 | | }, |
8576 | | { |
8577 | | MVM_OP_ordbaseat, |
8578 | | "ordbaseat", |
8579 | | " ", |
8580 | | 3, |
8581 | | 1, |
8582 | | 0, |
8583 | | 0, |
8584 | | 0, |
8585 | | 0, |
8586 | | 0, |
8587 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
8588 | | }, |
8589 | | { |
8590 | | MVM_OP_neverrepossess, |
8591 | | "neverrepossess", |
8592 | | " ", |
8593 | | 1, |
8594 | | 0, |
8595 | | 0, |
8596 | | 0, |
8597 | | 0, |
8598 | | 0, |
8599 | | 0, |
8600 | | { MVM_operand_read_reg | MVM_operand_obj } |
8601 | | }, |
8602 | | { |
8603 | | MVM_OP_scdisclaim, |
8604 | | "scdisclaim", |
8605 | | " ", |
8606 | | 1, |
8607 | | 0, |
8608 | | 0, |
8609 | | 0, |
8610 | | 0, |
8611 | | 0, |
8612 | | 0, |
8613 | | { MVM_operand_read_reg | MVM_operand_obj } |
8614 | | }, |
8615 | | { |
8616 | | MVM_OP_DEPRECATED_31, |
8617 | | "DEPRECATED_31", |
8618 | | " ", |
8619 | | 1, |
8620 | | 0, |
8621 | | 0, |
8622 | | 0, |
8623 | | 0, |
8624 | | 0, |
8625 | | 0, |
8626 | | { MVM_operand_write_reg | MVM_operand_obj } |
8627 | | }, |
8628 | | { |
8629 | | MVM_OP_atpos2d_i, |
8630 | | "atpos2d_i", |
8631 | | " ", |
8632 | | 4, |
8633 | | 1, |
8634 | | 0, |
8635 | | 0, |
8636 | | 0, |
8637 | | 0, |
8638 | | 0, |
8639 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8640 | | }, |
8641 | | { |
8642 | | MVM_OP_atpos2d_n, |
8643 | | "atpos2d_n", |
8644 | | " ", |
8645 | | 4, |
8646 | | 1, |
8647 | | 0, |
8648 | | 0, |
8649 | | 0, |
8650 | | 0, |
8651 | | 0, |
8652 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8653 | | }, |
8654 | | { |
8655 | | MVM_OP_atpos2d_s, |
8656 | | "atpos2d_s", |
8657 | | " ", |
8658 | | 4, |
8659 | | 1, |
8660 | | 0, |
8661 | | 0, |
8662 | | 0, |
8663 | | 0, |
8664 | | 0, |
8665 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8666 | | }, |
8667 | | { |
8668 | | MVM_OP_atpos2d_o, |
8669 | | "atpos2d_o", |
8670 | | " ", |
8671 | | 4, |
8672 | | 1, |
8673 | | 0, |
8674 | | 0, |
8675 | | 0, |
8676 | | 0, |
8677 | | 0, |
8678 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8679 | | }, |
8680 | | { |
8681 | | MVM_OP_atpos3d_i, |
8682 | | "atpos3d_i", |
8683 | | " ", |
8684 | | 5, |
8685 | | 1, |
8686 | | 0, |
8687 | | 0, |
8688 | | 0, |
8689 | | 0, |
8690 | | 0, |
8691 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8692 | | }, |
8693 | | { |
8694 | | MVM_OP_atpos3d_n, |
8695 | | "atpos3d_n", |
8696 | | " ", |
8697 | | 5, |
8698 | | 1, |
8699 | | 0, |
8700 | | 0, |
8701 | | 0, |
8702 | | 0, |
8703 | | 0, |
8704 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8705 | | }, |
8706 | | { |
8707 | | MVM_OP_atpos3d_s, |
8708 | | "atpos3d_s", |
8709 | | " ", |
8710 | | 5, |
8711 | | 1, |
8712 | | 0, |
8713 | | 0, |
8714 | | 0, |
8715 | | 0, |
8716 | | 0, |
8717 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8718 | | }, |
8719 | | { |
8720 | | MVM_OP_atpos3d_o, |
8721 | | "atpos3d_o", |
8722 | | " ", |
8723 | | 5, |
8724 | | 1, |
8725 | | 0, |
8726 | | 0, |
8727 | | 0, |
8728 | | 0, |
8729 | | 0, |
8730 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8731 | | }, |
8732 | | { |
8733 | | MVM_OP_atposnd_i, |
8734 | | "atposnd_i", |
8735 | | " ", |
8736 | | 3, |
8737 | | 1, |
8738 | | 0, |
8739 | | 0, |
8740 | | 0, |
8741 | | 0, |
8742 | | 0, |
8743 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8744 | | }, |
8745 | | { |
8746 | | MVM_OP_atposnd_n, |
8747 | | "atposnd_n", |
8748 | | " ", |
8749 | | 3, |
8750 | | 1, |
8751 | | 0, |
8752 | | 0, |
8753 | | 0, |
8754 | | 0, |
8755 | | 0, |
8756 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8757 | | }, |
8758 | | { |
8759 | | MVM_OP_atposnd_s, |
8760 | | "atposnd_s", |
8761 | | " ", |
8762 | | 3, |
8763 | | 1, |
8764 | | 0, |
8765 | | 0, |
8766 | | 0, |
8767 | | 0, |
8768 | | 0, |
8769 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8770 | | }, |
8771 | | { |
8772 | | MVM_OP_atposnd_o, |
8773 | | "atposnd_o", |
8774 | | " ", |
8775 | | 3, |
8776 | | 1, |
8777 | | 0, |
8778 | | 0, |
8779 | | 0, |
8780 | | 0, |
8781 | | 0, |
8782 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8783 | | }, |
8784 | | { |
8785 | | MVM_OP_bindpos2d_i, |
8786 | | "bindpos2d_i", |
8787 | | " ", |
8788 | | 4, |
8789 | | 0, |
8790 | | 0, |
8791 | | 0, |
8792 | | 0, |
8793 | | 0, |
8794 | | 0, |
8795 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8796 | | }, |
8797 | | { |
8798 | | MVM_OP_bindpos2d_n, |
8799 | | "bindpos2d_n", |
8800 | | " ", |
8801 | | 4, |
8802 | | 0, |
8803 | | 0, |
8804 | | 0, |
8805 | | 0, |
8806 | | 0, |
8807 | | 0, |
8808 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64 } |
8809 | | }, |
8810 | | { |
8811 | | MVM_OP_bindpos2d_s, |
8812 | | "bindpos2d_s", |
8813 | | " ", |
8814 | | 4, |
8815 | | 0, |
8816 | | 0, |
8817 | | 0, |
8818 | | 0, |
8819 | | 0, |
8820 | | 0, |
8821 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
8822 | | }, |
8823 | | { |
8824 | | MVM_OP_bindpos2d_o, |
8825 | | "bindpos2d_o", |
8826 | | " ", |
8827 | | 4, |
8828 | | 0, |
8829 | | 0, |
8830 | | 0, |
8831 | | 0, |
8832 | | 0, |
8833 | | 0, |
8834 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8835 | | }, |
8836 | | { |
8837 | | MVM_OP_bindpos3d_i, |
8838 | | "bindpos3d_i", |
8839 | | " ", |
8840 | | 5, |
8841 | | 0, |
8842 | | 0, |
8843 | | 0, |
8844 | | 0, |
8845 | | 0, |
8846 | | 0, |
8847 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
8848 | | }, |
8849 | | { |
8850 | | MVM_OP_bindpos3d_n, |
8851 | | "bindpos3d_n", |
8852 | | " ", |
8853 | | 5, |
8854 | | 0, |
8855 | | 0, |
8856 | | 0, |
8857 | | 0, |
8858 | | 0, |
8859 | | 0, |
8860 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_num64 } |
8861 | | }, |
8862 | | { |
8863 | | MVM_OP_bindpos3d_s, |
8864 | | "bindpos3d_s", |
8865 | | " ", |
8866 | | 5, |
8867 | | 0, |
8868 | | 0, |
8869 | | 0, |
8870 | | 0, |
8871 | | 0, |
8872 | | 0, |
8873 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str } |
8874 | | }, |
8875 | | { |
8876 | | MVM_OP_bindpos3d_o, |
8877 | | "bindpos3d_o", |
8878 | | " ", |
8879 | | 5, |
8880 | | 0, |
8881 | | 0, |
8882 | | 0, |
8883 | | 0, |
8884 | | 0, |
8885 | | 0, |
8886 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8887 | | }, |
8888 | | { |
8889 | | MVM_OP_bindposnd_i, |
8890 | | "bindposnd_i", |
8891 | | " ", |
8892 | | 3, |
8893 | | 0, |
8894 | | 0, |
8895 | | 0, |
8896 | | 0, |
8897 | | 0, |
8898 | | 0, |
8899 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
8900 | | }, |
8901 | | { |
8902 | | MVM_OP_bindposnd_n, |
8903 | | "bindposnd_n", |
8904 | | " ", |
8905 | | 3, |
8906 | | 0, |
8907 | | 0, |
8908 | | 0, |
8909 | | 0, |
8910 | | 0, |
8911 | | 0, |
8912 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64 } |
8913 | | }, |
8914 | | { |
8915 | | MVM_OP_bindposnd_s, |
8916 | | "bindposnd_s", |
8917 | | " ", |
8918 | | 3, |
8919 | | 0, |
8920 | | 0, |
8921 | | 0, |
8922 | | 0, |
8923 | | 0, |
8924 | | 0, |
8925 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
8926 | | }, |
8927 | | { |
8928 | | MVM_OP_bindposnd_o, |
8929 | | "bindposnd_o", |
8930 | | " ", |
8931 | | 3, |
8932 | | 0, |
8933 | | 0, |
8934 | | 0, |
8935 | | 0, |
8936 | | 0, |
8937 | | 0, |
8938 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8939 | | }, |
8940 | | { |
8941 | | MVM_OP_dimensions, |
8942 | | "dimensions", |
8943 | | " ", |
8944 | | 2, |
8945 | | 0, |
8946 | | 0, |
8947 | | 0, |
8948 | | 0, |
8949 | | 0, |
8950 | | 0, |
8951 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8952 | | }, |
8953 | | { |
8954 | | MVM_OP_setdimensions, |
8955 | | "setdimensions", |
8956 | | " ", |
8957 | | 2, |
8958 | | 0, |
8959 | | 0, |
8960 | | 0, |
8961 | | 0, |
8962 | | 0, |
8963 | | 0, |
8964 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8965 | | }, |
8966 | | { |
8967 | | MVM_OP_numdimensions, |
8968 | | "numdimensions", |
8969 | | " ", |
8970 | | 2, |
8971 | | 1, |
8972 | | 0, |
8973 | | 0, |
8974 | | 0, |
8975 | | 0, |
8976 | | 0, |
8977 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
8978 | | }, |
8979 | | { |
8980 | | MVM_OP_ctxcode, |
8981 | | "ctxcode", |
8982 | | " ", |
8983 | | 2, |
8984 | | 0, |
8985 | | 0, |
8986 | | 0, |
8987 | | 0, |
8988 | | 0, |
8989 | | 0, |
8990 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
8991 | | }, |
8992 | | { |
8993 | | MVM_OP_isrwcont, |
8994 | | "isrwcont", |
8995 | | " ", |
8996 | | 2, |
8997 | | 1, |
8998 | | 0, |
8999 | | 0, |
9000 | | 0, |
9001 | | 0, |
9002 | | 0, |
9003 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9004 | | }, |
9005 | | { |
9006 | | MVM_OP_fc, |
9007 | | "fc", |
9008 | | " ", |
9009 | | 2, |
9010 | | 1, |
9011 | | 0, |
9012 | | 0, |
9013 | | 0, |
9014 | | 0, |
9015 | | 0, |
9016 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
9017 | | }, |
9018 | | { |
9019 | | MVM_OP_DEPRECATED_25, |
9020 | | "DEPRECATED_25", |
9021 | | " ", |
9022 | | 2, |
9023 | | 0, |
9024 | | 0, |
9025 | | 0, |
9026 | | 0, |
9027 | | 0, |
9028 | | 0, |
9029 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9030 | | }, |
9031 | | { |
9032 | | MVM_OP_DEPRECATED_21, |
9033 | | "DEPRECATED_21", |
9034 | | " ", |
9035 | | 2, |
9036 | | 0, |
9037 | | 0, |
9038 | | 0, |
9039 | | 0, |
9040 | | 0, |
9041 | | 0, |
9042 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
9043 | | }, |
9044 | | { |
9045 | | MVM_OP_encoderep, |
9046 | | "encoderep", |
9047 | | " ", |
9048 | | 5, |
9049 | | 0, |
9050 | | 0, |
9051 | | 0, |
9052 | | 0, |
9053 | | 0, |
9054 | | 0, |
9055 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
9056 | | }, |
9057 | | { |
9058 | | MVM_OP_istty_fh, |
9059 | | "istty_fh", |
9060 | | " ", |
9061 | | 2, |
9062 | | 1, |
9063 | | 0, |
9064 | | 0, |
9065 | | 0, |
9066 | | 0, |
9067 | | 0, |
9068 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9069 | | }, |
9070 | | { |
9071 | | MVM_OP_multidimref_i, |
9072 | | "multidimref_i", |
9073 | | " ", |
9074 | | 3, |
9075 | | 1, |
9076 | | 0, |
9077 | | 0, |
9078 | | 0, |
9079 | | 0, |
9080 | | 0, |
9081 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9082 | | }, |
9083 | | { |
9084 | | MVM_OP_multidimref_n, |
9085 | | "multidimref_n", |
9086 | | " ", |
9087 | | 3, |
9088 | | 1, |
9089 | | 0, |
9090 | | 0, |
9091 | | 0, |
9092 | | 0, |
9093 | | 0, |
9094 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9095 | | }, |
9096 | | { |
9097 | | MVM_OP_multidimref_s, |
9098 | | "multidimref_s", |
9099 | | " ", |
9100 | | 3, |
9101 | | 1, |
9102 | | 0, |
9103 | | 0, |
9104 | | 0, |
9105 | | 0, |
9106 | | 0, |
9107 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9108 | | }, |
9109 | | { |
9110 | | MVM_OP_fileno_fh, |
9111 | | "fileno_fh", |
9112 | | " ", |
9113 | | 2, |
9114 | | 1, |
9115 | | 0, |
9116 | | 0, |
9117 | | 0, |
9118 | | 0, |
9119 | | 0, |
9120 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9121 | | }, |
9122 | | { |
9123 | | MVM_OP_asyncudp, |
9124 | | "asyncudp", |
9125 | | " ", |
9126 | | 7, |
9127 | | 0, |
9128 | | 0, |
9129 | | 0, |
9130 | | 0, |
9131 | | 0, |
9132 | | 0, |
9133 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9134 | | }, |
9135 | | { |
9136 | | MVM_OP_DEPRECATED_15, |
9137 | | "DEPRECATED_15", |
9138 | | " ", |
9139 | | 8, |
9140 | | 0, |
9141 | | 0, |
9142 | | 0, |
9143 | | 0, |
9144 | | 0, |
9145 | | 0, |
9146 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9147 | | }, |
9148 | | { |
9149 | | MVM_OP_asyncwritebytesto, |
9150 | | "asyncwritebytesto", |
9151 | | " ", |
9152 | | 8, |
9153 | | 0, |
9154 | | 0, |
9155 | | 0, |
9156 | | 0, |
9157 | | 0, |
9158 | | 0, |
9159 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9160 | | }, |
9161 | | { |
9162 | | MVM_OP_objprimbits, |
9163 | | "objprimbits", |
9164 | | " ", |
9165 | | 2, |
9166 | | 0, |
9167 | | 0, |
9168 | | 0, |
9169 | | 0, |
9170 | | 0, |
9171 | | 0, |
9172 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9173 | | }, |
9174 | | { |
9175 | | MVM_OP_objprimunsigned, |
9176 | | "objprimunsigned", |
9177 | | " ", |
9178 | | 2, |
9179 | | 0, |
9180 | | 0, |
9181 | | 0, |
9182 | | 0, |
9183 | | 0, |
9184 | | 0, |
9185 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9186 | | }, |
9187 | | { |
9188 | | MVM_OP_DEPRECATED_5, |
9189 | | "DEPRECATED_5", |
9190 | | " ", |
9191 | | 2, |
9192 | | 1, |
9193 | | 0, |
9194 | | 0, |
9195 | | 1, |
9196 | | 0, |
9197 | | 0, |
9198 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int32 } |
9199 | | }, |
9200 | | { |
9201 | | MVM_OP_DEPRECATED_6, |
9202 | | "DEPRECATED_6", |
9203 | | " ", |
9204 | | 2, |
9205 | | 1, |
9206 | | 0, |
9207 | | 0, |
9208 | | 1, |
9209 | | 0, |
9210 | | 0, |
9211 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int16 } |
9212 | | }, |
9213 | | { |
9214 | | MVM_OP_DEPRECATED_7, |
9215 | | "DEPRECATED_7", |
9216 | | " ", |
9217 | | 2, |
9218 | | 1, |
9219 | | 0, |
9220 | | 0, |
9221 | | 1, |
9222 | | 0, |
9223 | | 0, |
9224 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int8 } |
9225 | | }, |
9226 | | { |
9227 | | MVM_OP_DEPRECATED_8, |
9228 | | "DEPRECATED_8", |
9229 | | " ", |
9230 | | 2, |
9231 | | 1, |
9232 | | 0, |
9233 | | 0, |
9234 | | 1, |
9235 | | 0, |
9236 | | 0, |
9237 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num32 } |
9238 | | }, |
9239 | | { |
9240 | | MVM_OP_getlexref_i32, |
9241 | | "getlexref_i32", |
9242 | | " ", |
9243 | | 2, |
9244 | | 1, |
9245 | | 0, |
9246 | | 0, |
9247 | | 1, |
9248 | | 0, |
9249 | | 0, |
9250 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_int32 } |
9251 | | }, |
9252 | | { |
9253 | | MVM_OP_getlexref_i16, |
9254 | | "getlexref_i16", |
9255 | | " ", |
9256 | | 2, |
9257 | | 1, |
9258 | | 0, |
9259 | | 0, |
9260 | | 1, |
9261 | | 0, |
9262 | | 0, |
9263 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_int16 } |
9264 | | }, |
9265 | | { |
9266 | | MVM_OP_getlexref_i8, |
9267 | | "getlexref_i8", |
9268 | | " ", |
9269 | | 2, |
9270 | | 1, |
9271 | | 0, |
9272 | | 0, |
9273 | | 1, |
9274 | | 0, |
9275 | | 0, |
9276 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_int8 } |
9277 | | }, |
9278 | | { |
9279 | | MVM_OP_getlexref_n32, |
9280 | | "getlexref_n32", |
9281 | | " ", |
9282 | | 2, |
9283 | | 1, |
9284 | | 0, |
9285 | | 0, |
9286 | | 1, |
9287 | | 0, |
9288 | | 0, |
9289 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_num32 } |
9290 | | }, |
9291 | | { |
9292 | | MVM_OP_box_u, |
9293 | | "box_u", |
9294 | | " ", |
9295 | | 3, |
9296 | | 1, |
9297 | | 0, |
9298 | | 0, |
9299 | | 0, |
9300 | | 0, |
9301 | | 0, |
9302 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_obj } |
9303 | | }, |
9304 | | { |
9305 | | MVM_OP_unbox_u, |
9306 | | "unbox_u", |
9307 | | " ", |
9308 | | 2, |
9309 | | 1, |
9310 | | 0, |
9311 | | 0, |
9312 | | 0, |
9313 | | 0, |
9314 | | 0, |
9315 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_obj } |
9316 | | }, |
9317 | | { |
9318 | | MVM_OP_coerce_iu, |
9319 | | "coerce_iu", |
9320 | | " ", |
9321 | | 2, |
9322 | | 1, |
9323 | | 0, |
9324 | | 0, |
9325 | | 0, |
9326 | | 0, |
9327 | | 0, |
9328 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_int64 } |
9329 | | }, |
9330 | | { |
9331 | | MVM_OP_coerce_ui, |
9332 | | "coerce_ui", |
9333 | | " ", |
9334 | | 2, |
9335 | | 1, |
9336 | | 0, |
9337 | | 0, |
9338 | | 0, |
9339 | | 0, |
9340 | | 0, |
9341 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_uint64 } |
9342 | | }, |
9343 | | { |
9344 | | MVM_OP_coerce_nu, |
9345 | | "coerce_nu", |
9346 | | " ", |
9347 | | 2, |
9348 | | 1, |
9349 | | 0, |
9350 | | 0, |
9351 | | 0, |
9352 | | 0, |
9353 | | 0, |
9354 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_num64 } |
9355 | | }, |
9356 | | { |
9357 | | MVM_OP_coerce_un, |
9358 | | "coerce_un", |
9359 | | " ", |
9360 | | 2, |
9361 | | 1, |
9362 | | 0, |
9363 | | 0, |
9364 | | 0, |
9365 | | 0, |
9366 | | 0, |
9367 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_uint64 } |
9368 | | }, |
9369 | | { |
9370 | | MVM_OP_decont_u, |
9371 | | "decont_u", |
9372 | | " ", |
9373 | | 2, |
9374 | | 1, |
9375 | | 0, |
9376 | | 0, |
9377 | | 0, |
9378 | | 1, |
9379 | | 0, |
9380 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_obj } |
9381 | | }, |
9382 | | { |
9383 | | MVM_OP_DEPRECATED_9, |
9384 | | "DEPRECATED_9", |
9385 | | " ", |
9386 | | 2, |
9387 | | 1, |
9388 | | 0, |
9389 | | 0, |
9390 | | 1, |
9391 | | 0, |
9392 | | 0, |
9393 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_uint64 } |
9394 | | }, |
9395 | | { |
9396 | | MVM_OP_DEPRECATED_10, |
9397 | | "DEPRECATED_10", |
9398 | | " ", |
9399 | | 2, |
9400 | | 1, |
9401 | | 0, |
9402 | | 0, |
9403 | | 1, |
9404 | | 0, |
9405 | | 0, |
9406 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_uint32 } |
9407 | | }, |
9408 | | { |
9409 | | MVM_OP_DEPRECATED_11, |
9410 | | "DEPRECATED_11", |
9411 | | " ", |
9412 | | 2, |
9413 | | 1, |
9414 | | 0, |
9415 | | 0, |
9416 | | 1, |
9417 | | 0, |
9418 | | 0, |
9419 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_uint16 } |
9420 | | }, |
9421 | | { |
9422 | | MVM_OP_DEPRECATED_12, |
9423 | | "DEPRECATED_12", |
9424 | | " ", |
9425 | | 2, |
9426 | | 1, |
9427 | | 0, |
9428 | | 0, |
9429 | | 1, |
9430 | | 0, |
9431 | | 0, |
9432 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_uint8 } |
9433 | | }, |
9434 | | { |
9435 | | MVM_OP_getlexref_u, |
9436 | | "getlexref_u", |
9437 | | " ", |
9438 | | 2, |
9439 | | 1, |
9440 | | 0, |
9441 | | 0, |
9442 | | 1, |
9443 | | 0, |
9444 | | 0, |
9445 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_uint64 } |
9446 | | }, |
9447 | | { |
9448 | | MVM_OP_getlexref_u32, |
9449 | | "getlexref_u32", |
9450 | | " ", |
9451 | | 2, |
9452 | | 1, |
9453 | | 0, |
9454 | | 0, |
9455 | | 1, |
9456 | | 0, |
9457 | | 0, |
9458 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_uint32 } |
9459 | | }, |
9460 | | { |
9461 | | MVM_OP_getlexref_u16, |
9462 | | "getlexref_u16", |
9463 | | " ", |
9464 | | 2, |
9465 | | 1, |
9466 | | 0, |
9467 | | 0, |
9468 | | 1, |
9469 | | 0, |
9470 | | 0, |
9471 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_uint16 } |
9472 | | }, |
9473 | | { |
9474 | | MVM_OP_getlexref_u8, |
9475 | | "getlexref_u8", |
9476 | | " ", |
9477 | | 2, |
9478 | | 1, |
9479 | | 0, |
9480 | | 0, |
9481 | | 1, |
9482 | | 0, |
9483 | | 0, |
9484 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_uint8 } |
9485 | | }, |
9486 | | { |
9487 | | MVM_OP_param_rp_u, |
9488 | | "param_rp_u", |
9489 | | " ", |
9490 | | 2, |
9491 | | 1, |
9492 | | 0, |
9493 | | 0, |
9494 | | 1, |
9495 | | 0, |
9496 | | 0, |
9497 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_int16 } |
9498 | | }, |
9499 | | { |
9500 | | MVM_OP_param_op_u, |
9501 | | "param_op_u", |
9502 | | " ", |
9503 | | 3, |
9504 | | 1, |
9505 | | 0, |
9506 | | 0, |
9507 | | 1, |
9508 | | 0, |
9509 | | 0, |
9510 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_int16, MVM_operand_ins } |
9511 | | }, |
9512 | | { |
9513 | | MVM_OP_param_rn_u, |
9514 | | "param_rn_u", |
9515 | | " ", |
9516 | | 2, |
9517 | | 0, |
9518 | | 0, |
9519 | | 0, |
9520 | | 1, |
9521 | | 0, |
9522 | | 0, |
9523 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_str } |
9524 | | }, |
9525 | | { |
9526 | | MVM_OP_param_on_u, |
9527 | | "param_on_u", |
9528 | | " ", |
9529 | | 3, |
9530 | | 0, |
9531 | | 0, |
9532 | | 0, |
9533 | | 1, |
9534 | | 0, |
9535 | | 0, |
9536 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_str, MVM_operand_ins } |
9537 | | }, |
9538 | | { |
9539 | | MVM_OP_param_rn2_u, |
9540 | | "param_rn2_u", |
9541 | | " ", |
9542 | | 3, |
9543 | | 0, |
9544 | | 0, |
9545 | | 0, |
9546 | | 1, |
9547 | | 0, |
9548 | | 0, |
9549 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_str, MVM_operand_str } |
9550 | | }, |
9551 | | { |
9552 | | MVM_OP_param_on2_u, |
9553 | | "param_on2_u", |
9554 | | " ", |
9555 | | 4, |
9556 | | 0, |
9557 | | 0, |
9558 | | 0, |
9559 | | 1, |
9560 | | 0, |
9561 | | 0, |
9562 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_str, MVM_operand_str, MVM_operand_ins } |
9563 | | }, |
9564 | | { |
9565 | | MVM_OP_stat_time, |
9566 | | "stat_time", |
9567 | | " ", |
9568 | | 3, |
9569 | | 0, |
9570 | | 0, |
9571 | | 0, |
9572 | | 0, |
9573 | | 0, |
9574 | | 0, |
9575 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9576 | | }, |
9577 | | { |
9578 | | MVM_OP_lstat_time, |
9579 | | "lstat_time", |
9580 | | " ", |
9581 | | 3, |
9582 | | 0, |
9583 | | 0, |
9584 | | 0, |
9585 | | 0, |
9586 | | 0, |
9587 | | 0, |
9588 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9589 | | }, |
9590 | | { |
9591 | | MVM_OP_setdebugtypename, |
9592 | | "setdebugtypename", |
9593 | | " ", |
9594 | | 2, |
9595 | | 0, |
9596 | | 0, |
9597 | | 0, |
9598 | | 0, |
9599 | | 0, |
9600 | | 0, |
9601 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
9602 | | }, |
9603 | | { |
9604 | | MVM_OP_loadbytecodebuffer, |
9605 | | "loadbytecodebuffer", |
9606 | | " ", |
9607 | | 1, |
9608 | | 0, |
9609 | | 0, |
9610 | | 0, |
9611 | | 0, |
9612 | | 1, |
9613 | | 0, |
9614 | | { MVM_operand_read_reg | MVM_operand_obj } |
9615 | | }, |
9616 | | { |
9617 | | MVM_OP_loadbytecodefh, |
9618 | | "loadbytecodefh", |
9619 | | " ", |
9620 | | 2, |
9621 | | 0, |
9622 | | 0, |
9623 | | 0, |
9624 | | 0, |
9625 | | 1, |
9626 | | 0, |
9627 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
9628 | | }, |
9629 | | { |
9630 | | MVM_OP_throwpayloadlex, |
9631 | | "throwpayloadlex", |
9632 | | " ", |
9633 | | 3, |
9634 | | 0, |
9635 | | 0, |
9636 | | 0, |
9637 | | 0, |
9638 | | 2, |
9639 | | 0, |
9640 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9641 | | }, |
9642 | | { |
9643 | | MVM_OP_throwpayloadlexcaller, |
9644 | | "throwpayloadlexcaller", |
9645 | | " ", |
9646 | | 3, |
9647 | | 0, |
9648 | | 0, |
9649 | | 0, |
9650 | | 0, |
9651 | | 2, |
9652 | | 0, |
9653 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9654 | | }, |
9655 | | { |
9656 | | MVM_OP_lastexpayload, |
9657 | | "lastexpayload", |
9658 | | " ", |
9659 | | 1, |
9660 | | 0, |
9661 | | 0, |
9662 | | 0, |
9663 | | 0, |
9664 | | 0, |
9665 | | 0, |
9666 | | { MVM_operand_write_reg | MVM_operand_obj } |
9667 | | }, |
9668 | | { |
9669 | | MVM_OP_cancelnotify, |
9670 | | "cancelnotify", |
9671 | | " ", |
9672 | | 3, |
9673 | | 0, |
9674 | | 0, |
9675 | | 0, |
9676 | | 0, |
9677 | | 0, |
9678 | | 0, |
9679 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9680 | | }, |
9681 | | { |
9682 | | MVM_OP_decoderconfigure, |
9683 | | "decoderconfigure", |
9684 | | " ", |
9685 | | 3, |
9686 | | 0, |
9687 | | 0, |
9688 | | 0, |
9689 | | 0, |
9690 | | 0, |
9691 | | 0, |
9692 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
9693 | | }, |
9694 | | { |
9695 | | MVM_OP_decodersetlineseps, |
9696 | | "decodersetlineseps", |
9697 | | " ", |
9698 | | 2, |
9699 | | 0, |
9700 | | 0, |
9701 | | 0, |
9702 | | 0, |
9703 | | 0, |
9704 | | 0, |
9705 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9706 | | }, |
9707 | | { |
9708 | | MVM_OP_decoderaddbytes, |
9709 | | "decoderaddbytes", |
9710 | | " ", |
9711 | | 2, |
9712 | | 0, |
9713 | | 0, |
9714 | | 0, |
9715 | | 0, |
9716 | | 0, |
9717 | | 0, |
9718 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9719 | | }, |
9720 | | { |
9721 | | MVM_OP_decodertakechars, |
9722 | | "decodertakechars", |
9723 | | " ", |
9724 | | 3, |
9725 | | 0, |
9726 | | 0, |
9727 | | 0, |
9728 | | 0, |
9729 | | 0, |
9730 | | 0, |
9731 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
9732 | | }, |
9733 | | { |
9734 | | MVM_OP_decodertakeallchars, |
9735 | | "decodertakeallchars", |
9736 | | " ", |
9737 | | 2, |
9738 | | 0, |
9739 | | 0, |
9740 | | 0, |
9741 | | 0, |
9742 | | 0, |
9743 | | 0, |
9744 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
9745 | | }, |
9746 | | { |
9747 | | MVM_OP_decodertakeavailablechars, |
9748 | | "decodertakeavailablechars", |
9749 | | " ", |
9750 | | 2, |
9751 | | 0, |
9752 | | 0, |
9753 | | 0, |
9754 | | 0, |
9755 | | 0, |
9756 | | 0, |
9757 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
9758 | | }, |
9759 | | { |
9760 | | MVM_OP_decodertakeline, |
9761 | | "decodertakeline", |
9762 | | " ", |
9763 | | 4, |
9764 | | 0, |
9765 | | 0, |
9766 | | 0, |
9767 | | 0, |
9768 | | 0, |
9769 | | 0, |
9770 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
9771 | | }, |
9772 | | { |
9773 | | MVM_OP_decoderbytesavailable, |
9774 | | "decoderbytesavailable", |
9775 | | " ", |
9776 | | 2, |
9777 | | 1, |
9778 | | 0, |
9779 | | 0, |
9780 | | 0, |
9781 | | 0, |
9782 | | 0, |
9783 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9784 | | }, |
9785 | | { |
9786 | | MVM_OP_decodertakebytes, |
9787 | | "decodertakebytes", |
9788 | | " ", |
9789 | | 4, |
9790 | | 0, |
9791 | | 0, |
9792 | | 0, |
9793 | | 0, |
9794 | | 0, |
9795 | | 0, |
9796 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
9797 | | }, |
9798 | | { |
9799 | | MVM_OP_decoderempty, |
9800 | | "decoderempty", |
9801 | | " ", |
9802 | | 2, |
9803 | | 1, |
9804 | | 0, |
9805 | | 0, |
9806 | | 0, |
9807 | | 0, |
9808 | | 0, |
9809 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9810 | | }, |
9811 | | { |
9812 | | MVM_OP_indexingoptimized, |
9813 | | "indexingoptimized", |
9814 | | " ", |
9815 | | 2, |
9816 | | 1, |
9817 | | 0, |
9818 | | 0, |
9819 | | 0, |
9820 | | 0, |
9821 | | 0, |
9822 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
9823 | | }, |
9824 | | { |
9825 | | MVM_OP_captureinnerlex, |
9826 | | "captureinnerlex", |
9827 | | " ", |
9828 | | 1, |
9829 | | 0, |
9830 | | 0, |
9831 | | 0, |
9832 | | 1, |
9833 | | 0, |
9834 | | 0, |
9835 | | { MVM_operand_read_reg | MVM_operand_obj } |
9836 | | }, |
9837 | | { |
9838 | | MVM_OP_unicmp_s, |
9839 | | "unicmp_s", |
9840 | | " ", |
9841 | | 6, |
9842 | | 1, |
9843 | | 0, |
9844 | | 0, |
9845 | | 0, |
9846 | | 0, |
9847 | | 0, |
9848 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
9849 | | }, |
9850 | | { |
9851 | | MVM_OP_setdispatcherfor, |
9852 | | "setdispatcherfor", |
9853 | | " ", |
9854 | | 2, |
9855 | | 0, |
9856 | | 0, |
9857 | | 0, |
9858 | | 0, |
9859 | | 0, |
9860 | | 0, |
9861 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9862 | | }, |
9863 | | { |
9864 | | MVM_OP_getstrfromname, |
9865 | | "getstrfromname", |
9866 | | " ", |
9867 | | 2, |
9868 | | 1, |
9869 | | 0, |
9870 | | 0, |
9871 | | 0, |
9872 | | 0, |
9873 | | 0, |
9874 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str } |
9875 | | }, |
9876 | | { |
9877 | | MVM_OP_indexic_s, |
9878 | | "indexic_s", |
9879 | | " ", |
9880 | | 4, |
9881 | | 1, |
9882 | | 0, |
9883 | | 0, |
9884 | | 0, |
9885 | | 0, |
9886 | | 0, |
9887 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9888 | | }, |
9889 | | { |
9890 | | MVM_OP_getport_sk, |
9891 | | "getport_sk", |
9892 | | " ", |
9893 | | 2, |
9894 | | 0, |
9895 | | 0, |
9896 | | 0, |
9897 | | 0, |
9898 | | 0, |
9899 | | 0, |
9900 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
9901 | | }, |
9902 | | { |
9903 | | MVM_OP_cpucores, |
9904 | | "cpucores", |
9905 | | " ", |
9906 | | 1, |
9907 | | 1, |
9908 | | 0, |
9909 | | 0, |
9910 | | 0, |
9911 | | 0, |
9912 | | 0, |
9913 | | { MVM_operand_write_reg | MVM_operand_int64 } |
9914 | | }, |
9915 | | { |
9916 | | MVM_OP_eqaticim_s, |
9917 | | "eqaticim_s", |
9918 | | " ", |
9919 | | 4, |
9920 | | 1, |
9921 | | 0, |
9922 | | 0, |
9923 | | 0, |
9924 | | 0, |
9925 | | 0, |
9926 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9927 | | }, |
9928 | | { |
9929 | | MVM_OP_indexicim_s, |
9930 | | "indexicim_s", |
9931 | | " ", |
9932 | | 4, |
9933 | | 1, |
9934 | | 0, |
9935 | | 0, |
9936 | | 0, |
9937 | | 0, |
9938 | | 0, |
9939 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9940 | | }, |
9941 | | { |
9942 | | MVM_OP_decodertakecharseof, |
9943 | | "decodertakecharseof", |
9944 | | " ", |
9945 | | 3, |
9946 | | 0, |
9947 | | 0, |
9948 | | 0, |
9949 | | 0, |
9950 | | 0, |
9951 | | 0, |
9952 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
9953 | | }, |
9954 | | { |
9955 | | MVM_OP_indexim_s, |
9956 | | "indexim_s", |
9957 | | " ", |
9958 | | 4, |
9959 | | 1, |
9960 | | 0, |
9961 | | 0, |
9962 | | 0, |
9963 | | 0, |
9964 | | 0, |
9965 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
9966 | | }, |
9967 | | { |
9968 | | MVM_OP_cas_o, |
9969 | | "cas_o", |
9970 | | " ", |
9971 | | 4, |
9972 | | 0, |
9973 | | 0, |
9974 | | 0, |
9975 | | 0, |
9976 | | 1, |
9977 | | 0, |
9978 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
9979 | | }, |
9980 | | { |
9981 | | MVM_OP_cas_i, |
9982 | | "cas_i", |
9983 | | " ", |
9984 | | 4, |
9985 | | 0, |
9986 | | 0, |
9987 | | 0, |
9988 | | 0, |
9989 | | 0, |
9990 | | 0, |
9991 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
9992 | | }, |
9993 | | { |
9994 | | MVM_OP_atomicinc_i, |
9995 | | "atomicinc_i", |
9996 | | " ", |
9997 | | 2, |
9998 | | 0, |
9999 | | 0, |
10000 | | 0, |
10001 | | 0, |
10002 | | 0, |
10003 | | 0, |
10004 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
10005 | | }, |
10006 | | { |
10007 | | MVM_OP_atomicdec_i, |
10008 | | "atomicdec_i", |
10009 | | " ", |
10010 | | 2, |
10011 | | 0, |
10012 | | 0, |
10013 | | 0, |
10014 | | 0, |
10015 | | 0, |
10016 | | 0, |
10017 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
10018 | | }, |
10019 | | { |
10020 | | MVM_OP_atomicadd_i, |
10021 | | "atomicadd_i", |
10022 | | " ", |
10023 | | 3, |
10024 | | 0, |
10025 | | 0, |
10026 | | 0, |
10027 | | 0, |
10028 | | 0, |
10029 | | 0, |
10030 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
10031 | | }, |
10032 | | { |
10033 | | MVM_OP_atomicload_o, |
10034 | | "atomicload_o", |
10035 | | " ", |
10036 | | 2, |
10037 | | 0, |
10038 | | 0, |
10039 | | 0, |
10040 | | 0, |
10041 | | 0, |
10042 | | 0, |
10043 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10044 | | }, |
10045 | | { |
10046 | | MVM_OP_atomicload_i, |
10047 | | "atomicload_i", |
10048 | | " ", |
10049 | | 2, |
10050 | | 0, |
10051 | | 0, |
10052 | | 0, |
10053 | | 0, |
10054 | | 0, |
10055 | | 0, |
10056 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
10057 | | }, |
10058 | | { |
10059 | | MVM_OP_atomicstore_o, |
10060 | | "atomicstore_o", |
10061 | | " ", |
10062 | | 2, |
10063 | | 0, |
10064 | | 0, |
10065 | | 0, |
10066 | | 0, |
10067 | | 1, |
10068 | | 0, |
10069 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10070 | | }, |
10071 | | { |
10072 | | MVM_OP_atomicstore_i, |
10073 | | "atomicstore_i", |
10074 | | " ", |
10075 | | 2, |
10076 | | 0, |
10077 | | 0, |
10078 | | 0, |
10079 | | 0, |
10080 | | 0, |
10081 | | 0, |
10082 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
10083 | | }, |
10084 | | { |
10085 | | MVM_OP_barrierfull, |
10086 | | "barrierfull", |
10087 | | " ", |
10088 | | 0, |
10089 | | 0, |
10090 | | 0, |
10091 | | 0, |
10092 | | 0, |
10093 | | 0, |
10094 | | 0, |
10095 | | }, |
10096 | | { |
10097 | | MVM_OP_coveragecontrol, |
10098 | | "coveragecontrol", |
10099 | | " ", |
10100 | | 1, |
10101 | | 0, |
10102 | | 0, |
10103 | | 0, |
10104 | | 0, |
10105 | | 0, |
10106 | | 0, |
10107 | | { MVM_operand_read_reg | MVM_operand_int64 } |
10108 | | }, |
10109 | | { |
10110 | | MVM_OP_nativeinvoke_v, |
10111 | | "nativeinvoke_v", |
10112 | | "-a", |
10113 | | 2, |
10114 | | 0, |
10115 | | 0, |
10116 | | 0, |
10117 | | 0, |
10118 | | 0, |
10119 | | 0, |
10120 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10121 | | }, |
10122 | | { |
10123 | | MVM_OP_nativeinvoke_i, |
10124 | | "nativeinvoke_i", |
10125 | | "-a", |
10126 | | 3, |
10127 | | 0, |
10128 | | 0, |
10129 | | 0, |
10130 | | 0, |
10131 | | 0, |
10132 | | 0, |
10133 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10134 | | }, |
10135 | | { |
10136 | | MVM_OP_nativeinvoke_n, |
10137 | | "nativeinvoke_n", |
10138 | | "-a", |
10139 | | 3, |
10140 | | 0, |
10141 | | 0, |
10142 | | 0, |
10143 | | 0, |
10144 | | 0, |
10145 | | 0, |
10146 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10147 | | }, |
10148 | | { |
10149 | | MVM_OP_nativeinvoke_s, |
10150 | | "nativeinvoke_s", |
10151 | | "-a", |
10152 | | 3, |
10153 | | 0, |
10154 | | 0, |
10155 | | 0, |
10156 | | 0, |
10157 | | 0, |
10158 | | 0, |
10159 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10160 | | }, |
10161 | | { |
10162 | | MVM_OP_nativeinvoke_o, |
10163 | | "nativeinvoke_o", |
10164 | | "-a", |
10165 | | 3, |
10166 | | 0, |
10167 | | 0, |
10168 | | 0, |
10169 | | 0, |
10170 | | 0, |
10171 | | 0, |
10172 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10173 | | }, |
10174 | | { |
10175 | | MVM_OP_getarg_i, |
10176 | | "getarg_i", |
10177 | | " ", |
10178 | | 2, |
10179 | | 0, |
10180 | | 0, |
10181 | | 0, |
10182 | | 0, |
10183 | | 0, |
10184 | | 0, |
10185 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int16 } |
10186 | | }, |
10187 | | { |
10188 | | MVM_OP_getarg_n, |
10189 | | "getarg_n", |
10190 | | " ", |
10191 | | 2, |
10192 | | 0, |
10193 | | 0, |
10194 | | 0, |
10195 | | 0, |
10196 | | 0, |
10197 | | 0, |
10198 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_int16 } |
10199 | | }, |
10200 | | { |
10201 | | MVM_OP_getarg_s, |
10202 | | "getarg_s", |
10203 | | " ", |
10204 | | 2, |
10205 | | 0, |
10206 | | 0, |
10207 | | 0, |
10208 | | 0, |
10209 | | 0, |
10210 | | 0, |
10211 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int16 } |
10212 | | }, |
10213 | | { |
10214 | | MVM_OP_getarg_o, |
10215 | | "getarg_o", |
10216 | | " ", |
10217 | | 2, |
10218 | | 0, |
10219 | | 0, |
10220 | | 0, |
10221 | | 0, |
10222 | | 0, |
10223 | | 0, |
10224 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int16 } |
10225 | | }, |
10226 | | { |
10227 | | MVM_OP_coerce_II, |
10228 | | "coerce_II", |
10229 | | " ", |
10230 | | 3, |
10231 | | 1, |
10232 | | 0, |
10233 | | 0, |
10234 | | 0, |
10235 | | 0, |
10236 | | 0, |
10237 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10238 | | }, |
10239 | | { |
10240 | | MVM_OP_encoderepconf, |
10241 | | "encoderepconf", |
10242 | | " ", |
10243 | | 6, |
10244 | | 0, |
10245 | | 0, |
10246 | | 0, |
10247 | | 0, |
10248 | | 0, |
10249 | | 0, |
10250 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
10251 | | }, |
10252 | | { |
10253 | | MVM_OP_encodeconf, |
10254 | | "encodeconf", |
10255 | | " ", |
10256 | | 5, |
10257 | | 0, |
10258 | | 0, |
10259 | | 0, |
10260 | | 0, |
10261 | | 0, |
10262 | | 0, |
10263 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64 } |
10264 | | }, |
10265 | | { |
10266 | | MVM_OP_decodeconf, |
10267 | | "decodeconf", |
10268 | | " ", |
10269 | | 4, |
10270 | | 0, |
10271 | | 0, |
10272 | | 0, |
10273 | | 0, |
10274 | | 0, |
10275 | | 0, |
10276 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
10277 | | }, |
10278 | | { |
10279 | | MVM_OP_decoderepconf, |
10280 | | "decoderepconf", |
10281 | | " ", |
10282 | | 5, |
10283 | | 0, |
10284 | | 0, |
10285 | | 0, |
10286 | | 0, |
10287 | | 0, |
10288 | | 0, |
10289 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_int64 } |
10290 | | }, |
10291 | | { |
10292 | | MVM_OP_getppid, |
10293 | | "getppid", |
10294 | | " ", |
10295 | | 1, |
10296 | | 0, |
10297 | | 0, |
10298 | | 0, |
10299 | | 0, |
10300 | | 0, |
10301 | | 0, |
10302 | | { MVM_operand_write_reg | MVM_operand_int64 } |
10303 | | }, |
10304 | | { |
10305 | | MVM_OP_getsignals, |
10306 | | "getsignals", |
10307 | | " ", |
10308 | | 1, |
10309 | | 0, |
10310 | | 0, |
10311 | | 0, |
10312 | | 0, |
10313 | | 0, |
10314 | | 1, |
10315 | | { MVM_operand_write_reg | MVM_operand_obj } |
10316 | | }, |
10317 | | { |
10318 | | MVM_OP_slice, |
10319 | | "slice", |
10320 | | " ", |
10321 | | 4, |
10322 | | 0, |
10323 | | 0, |
10324 | | 0, |
10325 | | 0, |
10326 | | 0, |
10327 | | 0, |
10328 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_int64 } |
10329 | | }, |
10330 | | { |
10331 | | MVM_OP_speshreg, |
10332 | | "speshreg", |
10333 | | " ", |
10334 | | 3, |
10335 | | 0, |
10336 | | 0, |
10337 | | 0, |
10338 | | 0, |
10339 | | 0, |
10340 | | 0, |
10341 | | { MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
10342 | | }, |
10343 | | { |
10344 | | MVM_OP_speshresolve, |
10345 | | "speshresolve", |
10346 | | "-a", |
10347 | | 2, |
10348 | | 0, |
10349 | | 1, |
10350 | | 1, |
10351 | | 1, |
10352 | | 0, |
10353 | | 0, |
10354 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
10355 | | }, |
10356 | | { |
10357 | | MVM_OP_speshguardtype, |
10358 | | "speshguardtype", |
10359 | | " ", |
10360 | | 2, |
10361 | | 0, |
10362 | | 0, |
10363 | | 0, |
10364 | | 0, |
10365 | | 0, |
10366 | | 0, |
10367 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10368 | | }, |
10369 | | { |
10370 | | MVM_OP_speshguardconcrete, |
10371 | | "speshguardconcrete", |
10372 | | " ", |
10373 | | 1, |
10374 | | 0, |
10375 | | 0, |
10376 | | 0, |
10377 | | 0, |
10378 | | 0, |
10379 | | 0, |
10380 | | { MVM_operand_read_reg | MVM_operand_obj } |
10381 | | }, |
10382 | | { |
10383 | | MVM_OP_speshguardtypeobj, |
10384 | | "speshguardtypeobj", |
10385 | | " ", |
10386 | | 1, |
10387 | | 0, |
10388 | | 0, |
10389 | | 0, |
10390 | | 0, |
10391 | | 0, |
10392 | | 0, |
10393 | | { MVM_operand_read_reg | MVM_operand_obj } |
10394 | | }, |
10395 | | { |
10396 | | MVM_OP_speshguardobj, |
10397 | | "speshguardobj", |
10398 | | " ", |
10399 | | 1, |
10400 | | 0, |
10401 | | 0, |
10402 | | 0, |
10403 | | 0, |
10404 | | 0, |
10405 | | 0, |
10406 | | { MVM_operand_read_reg | MVM_operand_obj } |
10407 | | }, |
10408 | | { |
10409 | | MVM_OP_speshguardgetattr, |
10410 | | "speshguardgetattr", |
10411 | | " ", |
10412 | | 4, |
10413 | | 0, |
10414 | | 0, |
10415 | | 0, |
10416 | | 0, |
10417 | | 0, |
10418 | | 0, |
10419 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str } |
10420 | | }, |
10421 | | { |
10422 | | MVM_OP_atomicbindattr_o, |
10423 | | "atomicbindattr_o", |
10424 | | " ", |
10425 | | 4, |
10426 | | 0, |
10427 | | 0, |
10428 | | 0, |
10429 | | 0, |
10430 | | 0, |
10431 | | 0, |
10432 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj } |
10433 | | }, |
10434 | | { |
10435 | | MVM_OP_casattr_o, |
10436 | | "casattr_o", |
10437 | | " ", |
10438 | | 6, |
10439 | | 0, |
10440 | | 0, |
10441 | | 0, |
10442 | | 0, |
10443 | | 0, |
10444 | | 0, |
10445 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10446 | | }, |
10447 | | { |
10448 | | MVM_OP_atkey_u, |
10449 | | "atkey_u", |
10450 | | " ", |
10451 | | 3, |
10452 | | 0, |
10453 | | 0, |
10454 | | 0, |
10455 | | 0, |
10456 | | 0, |
10457 | | 0, |
10458 | | { MVM_operand_write_reg | MVM_operand_uint64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_str } |
10459 | | }, |
10460 | | { |
10461 | | MVM_OP_coerce_us, |
10462 | | "coerce_us", |
10463 | | " ", |
10464 | | 2, |
10465 | | 1, |
10466 | | 0, |
10467 | | 0, |
10468 | | 0, |
10469 | | 0, |
10470 | | 0, |
10471 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_uint64 } |
10472 | | }, |
10473 | | { |
10474 | | MVM_OP_speshguardnotobj, |
10475 | | "speshguardnotobj", |
10476 | | " ", |
10477 | | 2, |
10478 | | 0, |
10479 | | 0, |
10480 | | 0, |
10481 | | 0, |
10482 | | 0, |
10483 | | 0, |
10484 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10485 | | }, |
10486 | | { |
10487 | | MVM_OP_sp_guard, |
10488 | | "sp_guard", |
10489 | | ".s", |
10490 | | 3, |
10491 | | 0, |
10492 | | 0, |
10493 | | 0, |
10494 | | 0, |
10495 | | 0, |
10496 | | 0, |
10497 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10498 | | }, |
10499 | | { |
10500 | | MVM_OP_sp_guardconc, |
10501 | | "sp_guardconc", |
10502 | | ".s", |
10503 | | 3, |
10504 | | 0, |
10505 | | 0, |
10506 | | 0, |
10507 | | 0, |
10508 | | 0, |
10509 | | 0, |
10510 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10511 | | }, |
10512 | | { |
10513 | | MVM_OP_sp_guardtype, |
10514 | | "sp_guardtype", |
10515 | | ".s", |
10516 | | 3, |
10517 | | 0, |
10518 | | 0, |
10519 | | 0, |
10520 | | 0, |
10521 | | 0, |
10522 | | 0, |
10523 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10524 | | }, |
10525 | | { |
10526 | | MVM_OP_sp_guardsf, |
10527 | | "sp_guardsf", |
10528 | | ".s", |
10529 | | 3, |
10530 | | 0, |
10531 | | 0, |
10532 | | 0, |
10533 | | 0, |
10534 | | 0, |
10535 | | 0, |
10536 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10537 | | }, |
10538 | | { |
10539 | | MVM_OP_sp_guardsfouter, |
10540 | | "sp_guardsfouter", |
10541 | | ".s", |
10542 | | 3, |
10543 | | 0, |
10544 | | 0, |
10545 | | 0, |
10546 | | 0, |
10547 | | 0, |
10548 | | 0, |
10549 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10550 | | }, |
10551 | | { |
10552 | | MVM_OP_sp_guardobj, |
10553 | | "sp_guardobj", |
10554 | | ".s", |
10555 | | 3, |
10556 | | 0, |
10557 | | 0, |
10558 | | 0, |
10559 | | 0, |
10560 | | 0, |
10561 | | 0, |
10562 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10563 | | }, |
10564 | | { |
10565 | | MVM_OP_sp_guardnotobj, |
10566 | | "sp_guardnotobj", |
10567 | | ".s", |
10568 | | 3, |
10569 | | 0, |
10570 | | 0, |
10571 | | 0, |
10572 | | 0, |
10573 | | 0, |
10574 | | 0, |
10575 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_uint32 } |
10576 | | }, |
10577 | | { |
10578 | | MVM_OP_sp_guardjustconc, |
10579 | | "sp_guardjustconc", |
10580 | | ".s", |
10581 | | 2, |
10582 | | 0, |
10583 | | 0, |
10584 | | 0, |
10585 | | 0, |
10586 | | 0, |
10587 | | 0, |
10588 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_uint32 } |
10589 | | }, |
10590 | | { |
10591 | | MVM_OP_sp_guardjusttype, |
10592 | | "sp_guardjusttype", |
10593 | | ".s", |
10594 | | 2, |
10595 | | 0, |
10596 | | 0, |
10597 | | 0, |
10598 | | 0, |
10599 | | 0, |
10600 | | 0, |
10601 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_uint32 } |
10602 | | }, |
10603 | | { |
10604 | | MVM_OP_sp_rebless, |
10605 | | "sp_rebless", |
10606 | | ".s", |
10607 | | 4, |
10608 | | 0, |
10609 | | 0, |
10610 | | 0, |
10611 | | 1, |
10612 | | 0, |
10613 | | 0, |
10614 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_uint32 } |
10615 | | }, |
10616 | | { |
10617 | | MVM_OP_sp_resolvecode, |
10618 | | "sp_resolvecode", |
10619 | | ".s", |
10620 | | 2, |
10621 | | 0, |
10622 | | 0, |
10623 | | 0, |
10624 | | 0, |
10625 | | 0, |
10626 | | 0, |
10627 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10628 | | }, |
10629 | | { |
10630 | | MVM_OP_sp_decont, |
10631 | | "sp_decont", |
10632 | | ".s", |
10633 | | 2, |
10634 | | 1, |
10635 | | 0, |
10636 | | 0, |
10637 | | 0, |
10638 | | 1, |
10639 | | 0, |
10640 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
10641 | | }, |
10642 | | { |
10643 | | MVM_OP_sp_getlex_o, |
10644 | | "sp_getlex_o", |
10645 | | ".s", |
10646 | | 2, |
10647 | | 1, |
10648 | | 0, |
10649 | | 0, |
10650 | | 0, |
10651 | | 0, |
10652 | | 0, |
10653 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_lex | MVM_operand_obj } |
10654 | | }, |
10655 | | { |
10656 | | MVM_OP_sp_getlex_ins, |
10657 | | "sp_getlex_ins", |
10658 | | ".s", |
10659 | | 2, |
10660 | | 1, |
10661 | | 0, |
10662 | | 0, |
10663 | | 0, |
10664 | | 0, |
10665 | | 0, |
10666 | | { MVM_operand_write_reg | MVM_operand_type_var, MVM_operand_read_lex | MVM_operand_type_var } |
10667 | | }, |
10668 | | { |
10669 | | MVM_OP_sp_getlex_no, |
10670 | | "sp_getlex_no", |
10671 | | ".s", |
10672 | | 2, |
10673 | | 1, |
10674 | | 0, |
10675 | | 0, |
10676 | | 1, |
10677 | | 0, |
10678 | | 0, |
10679 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str } |
10680 | | }, |
10681 | | { |
10682 | | MVM_OP_sp_getarg_o, |
10683 | | "sp_getarg_o", |
10684 | | ".s", |
10685 | | 2, |
10686 | | 1, |
10687 | | 0, |
10688 | | 0, |
10689 | | 0, |
10690 | | 0, |
10691 | | 0, |
10692 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16 } |
10693 | | }, |
10694 | | { |
10695 | | MVM_OP_sp_getarg_i, |
10696 | | "sp_getarg_i", |
10697 | | ".s", |
10698 | | 2, |
10699 | | 1, |
10700 | | 0, |
10701 | | 0, |
10702 | | 0, |
10703 | | 0, |
10704 | | 0, |
10705 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16 } |
10706 | | }, |
10707 | | { |
10708 | | MVM_OP_sp_getarg_n, |
10709 | | "sp_getarg_n", |
10710 | | ".s", |
10711 | | 2, |
10712 | | 1, |
10713 | | 0, |
10714 | | 0, |
10715 | | 0, |
10716 | | 0, |
10717 | | 0, |
10718 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16 } |
10719 | | }, |
10720 | | { |
10721 | | MVM_OP_sp_getarg_s, |
10722 | | "sp_getarg_s", |
10723 | | ".s", |
10724 | | 2, |
10725 | | 1, |
10726 | | 0, |
10727 | | 0, |
10728 | | 0, |
10729 | | 0, |
10730 | | 0, |
10731 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16 } |
10732 | | }, |
10733 | | { |
10734 | | MVM_OP_sp_fastinvoke_v, |
10735 | | "sp_fastinvoke_v", |
10736 | | ".s", |
10737 | | 2, |
10738 | | 0, |
10739 | | 0, |
10740 | | 0, |
10741 | | 0, |
10742 | | 0, |
10743 | | 0, |
10744 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10745 | | }, |
10746 | | { |
10747 | | MVM_OP_sp_fastinvoke_i, |
10748 | | "sp_fastinvoke_i", |
10749 | | ".s", |
10750 | | 3, |
10751 | | 0, |
10752 | | 0, |
10753 | | 0, |
10754 | | 0, |
10755 | | 0, |
10756 | | 0, |
10757 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10758 | | }, |
10759 | | { |
10760 | | MVM_OP_sp_fastinvoke_n, |
10761 | | "sp_fastinvoke_n", |
10762 | | ".s", |
10763 | | 3, |
10764 | | 0, |
10765 | | 0, |
10766 | | 0, |
10767 | | 0, |
10768 | | 0, |
10769 | | 0, |
10770 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10771 | | }, |
10772 | | { |
10773 | | MVM_OP_sp_fastinvoke_s, |
10774 | | "sp_fastinvoke_s", |
10775 | | ".s", |
10776 | | 3, |
10777 | | 0, |
10778 | | 0, |
10779 | | 0, |
10780 | | 0, |
10781 | | 0, |
10782 | | 0, |
10783 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10784 | | }, |
10785 | | { |
10786 | | MVM_OP_sp_fastinvoke_o, |
10787 | | "sp_fastinvoke_o", |
10788 | | ".s", |
10789 | | 3, |
10790 | | 0, |
10791 | | 0, |
10792 | | 0, |
10793 | | 0, |
10794 | | 0, |
10795 | | 0, |
10796 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10797 | | }, |
10798 | | { |
10799 | | MVM_OP_sp_speshresolve, |
10800 | | "sp_speshresolve", |
10801 | | " ", |
10802 | | 4, |
10803 | | 0, |
10804 | | 0, |
10805 | | 0, |
10806 | | 0, |
10807 | | 0, |
10808 | | 0, |
10809 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_uint32, MVM_operand_spesh_slot } |
10810 | | }, |
10811 | | { |
10812 | | MVM_OP_sp_paramnamesused, |
10813 | | "sp_paramnamesused", |
10814 | | " ", |
10815 | | 1, |
10816 | | 0, |
10817 | | 0, |
10818 | | 0, |
10819 | | 0, |
10820 | | 0, |
10821 | | 0, |
10822 | | { MVM_operand_spesh_slot } |
10823 | | }, |
10824 | | { |
10825 | | MVM_OP_sp_getspeshslot, |
10826 | | "sp_getspeshslot", |
10827 | | ".s", |
10828 | | 2, |
10829 | | 1, |
10830 | | 0, |
10831 | | 0, |
10832 | | 0, |
10833 | | 0, |
10834 | | 0, |
10835 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_spesh_slot } |
10836 | | }, |
10837 | | { |
10838 | | MVM_OP_sp_findmeth, |
10839 | | "sp_findmeth", |
10840 | | ".s", |
10841 | | 4, |
10842 | | 1, |
10843 | | 0, |
10844 | | 0, |
10845 | | 0, |
10846 | | 0, |
10847 | | 0, |
10848 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_str, MVM_operand_spesh_slot } |
10849 | | }, |
10850 | | { |
10851 | | MVM_OP_sp_fastcreate, |
10852 | | "sp_fastcreate", |
10853 | | ".s", |
10854 | | 3, |
10855 | | 1, |
10856 | | 0, |
10857 | | 0, |
10858 | | 0, |
10859 | | 0, |
10860 | | 0, |
10861 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_spesh_slot } |
10862 | | }, |
10863 | | { |
10864 | | MVM_OP_sp_get_o, |
10865 | | "sp_get_o", |
10866 | | ".s", |
10867 | | 3, |
10868 | | 1, |
10869 | | 0, |
10870 | | 0, |
10871 | | 0, |
10872 | | 0, |
10873 | | 0, |
10874 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10875 | | }, |
10876 | | { |
10877 | | MVM_OP_sp_get_i64, |
10878 | | "sp_get_i64", |
10879 | | ".s", |
10880 | | 3, |
10881 | | 1, |
10882 | | 0, |
10883 | | 0, |
10884 | | 0, |
10885 | | 0, |
10886 | | 0, |
10887 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10888 | | }, |
10889 | | { |
10890 | | MVM_OP_sp_get_i32, |
10891 | | "sp_get_i32", |
10892 | | ".s", |
10893 | | 3, |
10894 | | 1, |
10895 | | 0, |
10896 | | 0, |
10897 | | 0, |
10898 | | 0, |
10899 | | 0, |
10900 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10901 | | }, |
10902 | | { |
10903 | | MVM_OP_sp_get_i16, |
10904 | | "sp_get_i16", |
10905 | | ".s", |
10906 | | 3, |
10907 | | 1, |
10908 | | 0, |
10909 | | 0, |
10910 | | 0, |
10911 | | 0, |
10912 | | 0, |
10913 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10914 | | }, |
10915 | | { |
10916 | | MVM_OP_sp_get_i8, |
10917 | | "sp_get_i8", |
10918 | | ".s", |
10919 | | 3, |
10920 | | 1, |
10921 | | 0, |
10922 | | 0, |
10923 | | 0, |
10924 | | 0, |
10925 | | 0, |
10926 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10927 | | }, |
10928 | | { |
10929 | | MVM_OP_sp_get_n, |
10930 | | "sp_get_n", |
10931 | | ".s", |
10932 | | 3, |
10933 | | 1, |
10934 | | 0, |
10935 | | 0, |
10936 | | 0, |
10937 | | 0, |
10938 | | 0, |
10939 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10940 | | }, |
10941 | | { |
10942 | | MVM_OP_sp_get_s, |
10943 | | "sp_get_s", |
10944 | | ".s", |
10945 | | 3, |
10946 | | 1, |
10947 | | 0, |
10948 | | 0, |
10949 | | 0, |
10950 | | 0, |
10951 | | 0, |
10952 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
10953 | | }, |
10954 | | { |
10955 | | MVM_OP_sp_bind_o, |
10956 | | "sp_bind_o", |
10957 | | ".s", |
10958 | | 3, |
10959 | | 0, |
10960 | | 0, |
10961 | | 0, |
10962 | | 0, |
10963 | | 0, |
10964 | | 0, |
10965 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_obj } |
10966 | | }, |
10967 | | { |
10968 | | MVM_OP_sp_bind_i64, |
10969 | | "sp_bind_i64", |
10970 | | ".s", |
10971 | | 3, |
10972 | | 0, |
10973 | | 0, |
10974 | | 0, |
10975 | | 0, |
10976 | | 0, |
10977 | | 0, |
10978 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
10979 | | }, |
10980 | | { |
10981 | | MVM_OP_sp_bind_i32, |
10982 | | "sp_bind_i32", |
10983 | | ".s", |
10984 | | 3, |
10985 | | 0, |
10986 | | 0, |
10987 | | 0, |
10988 | | 0, |
10989 | | 0, |
10990 | | 0, |
10991 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
10992 | | }, |
10993 | | { |
10994 | | MVM_OP_sp_bind_i16, |
10995 | | "sp_bind_i16", |
10996 | | ".s", |
10997 | | 3, |
10998 | | 0, |
10999 | | 0, |
11000 | | 0, |
11001 | | 0, |
11002 | | 0, |
11003 | | 0, |
11004 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
11005 | | }, |
11006 | | { |
11007 | | MVM_OP_sp_bind_i8, |
11008 | | "sp_bind_i8", |
11009 | | ".s", |
11010 | | 3, |
11011 | | 0, |
11012 | | 0, |
11013 | | 0, |
11014 | | 0, |
11015 | | 0, |
11016 | | 0, |
11017 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
11018 | | }, |
11019 | | { |
11020 | | MVM_OP_sp_bind_n, |
11021 | | "sp_bind_n", |
11022 | | ".s", |
11023 | | 3, |
11024 | | 0, |
11025 | | 0, |
11026 | | 0, |
11027 | | 0, |
11028 | | 0, |
11029 | | 0, |
11030 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_num64 } |
11031 | | }, |
11032 | | { |
11033 | | MVM_OP_sp_bind_s, |
11034 | | "sp_bind_s", |
11035 | | ".s", |
11036 | | 3, |
11037 | | 0, |
11038 | | 0, |
11039 | | 0, |
11040 | | 0, |
11041 | | 0, |
11042 | | 0, |
11043 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_str } |
11044 | | }, |
11045 | | { |
11046 | | MVM_OP_sp_p6oget_o, |
11047 | | "sp_p6oget_o", |
11048 | | ".s", |
11049 | | 3, |
11050 | | 1, |
11051 | | 0, |
11052 | | 0, |
11053 | | 0, |
11054 | | 0, |
11055 | | 0, |
11056 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11057 | | }, |
11058 | | { |
11059 | | MVM_OP_sp_p6ogetvt_o, |
11060 | | "sp_p6ogetvt_o", |
11061 | | ".s", |
11062 | | 4, |
11063 | | 0, |
11064 | | 0, |
11065 | | 0, |
11066 | | 0, |
11067 | | 0, |
11068 | | 0, |
11069 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_spesh_slot } |
11070 | | }, |
11071 | | { |
11072 | | MVM_OP_sp_p6ogetvc_o, |
11073 | | "sp_p6ogetvc_o", |
11074 | | ".s", |
11075 | | 4, |
11076 | | 0, |
11077 | | 0, |
11078 | | 0, |
11079 | | 0, |
11080 | | 0, |
11081 | | 0, |
11082 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_spesh_slot } |
11083 | | }, |
11084 | | { |
11085 | | MVM_OP_sp_p6oget_i, |
11086 | | "sp_p6oget_i", |
11087 | | ".s", |
11088 | | 3, |
11089 | | 1, |
11090 | | 0, |
11091 | | 0, |
11092 | | 0, |
11093 | | 0, |
11094 | | 0, |
11095 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11096 | | }, |
11097 | | { |
11098 | | MVM_OP_sp_p6oget_n, |
11099 | | "sp_p6oget_n", |
11100 | | ".s", |
11101 | | 3, |
11102 | | 1, |
11103 | | 0, |
11104 | | 0, |
11105 | | 0, |
11106 | | 0, |
11107 | | 0, |
11108 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11109 | | }, |
11110 | | { |
11111 | | MVM_OP_sp_p6oget_s, |
11112 | | "sp_p6oget_s", |
11113 | | ".s", |
11114 | | 3, |
11115 | | 1, |
11116 | | 0, |
11117 | | 0, |
11118 | | 0, |
11119 | | 0, |
11120 | | 0, |
11121 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11122 | | }, |
11123 | | { |
11124 | | MVM_OP_sp_p6obind_o, |
11125 | | "sp_p6obind_o", |
11126 | | ".s", |
11127 | | 3, |
11128 | | 0, |
11129 | | 0, |
11130 | | 0, |
11131 | | 0, |
11132 | | 0, |
11133 | | 0, |
11134 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_obj } |
11135 | | }, |
11136 | | { |
11137 | | MVM_OP_sp_p6obind_i, |
11138 | | "sp_p6obind_i", |
11139 | | ".s", |
11140 | | 3, |
11141 | | 0, |
11142 | | 0, |
11143 | | 0, |
11144 | | 0, |
11145 | | 0, |
11146 | | 0, |
11147 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_int64 } |
11148 | | }, |
11149 | | { |
11150 | | MVM_OP_sp_p6obind_n, |
11151 | | "sp_p6obind_n", |
11152 | | ".s", |
11153 | | 3, |
11154 | | 0, |
11155 | | 0, |
11156 | | 0, |
11157 | | 0, |
11158 | | 0, |
11159 | | 0, |
11160 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_num64 } |
11161 | | }, |
11162 | | { |
11163 | | MVM_OP_sp_p6obind_s, |
11164 | | "sp_p6obind_s", |
11165 | | ".s", |
11166 | | 3, |
11167 | | 0, |
11168 | | 0, |
11169 | | 0, |
11170 | | 0, |
11171 | | 0, |
11172 | | 0, |
11173 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_str } |
11174 | | }, |
11175 | | { |
11176 | | MVM_OP_sp_deref_get_i64, |
11177 | | "sp_deref_get_i64", |
11178 | | ".s", |
11179 | | 3, |
11180 | | 1, |
11181 | | 0, |
11182 | | 0, |
11183 | | 0, |
11184 | | 0, |
11185 | | 0, |
11186 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11187 | | }, |
11188 | | { |
11189 | | MVM_OP_sp_deref_get_n, |
11190 | | "sp_deref_get_n", |
11191 | | ".s", |
11192 | | 3, |
11193 | | 1, |
11194 | | 0, |
11195 | | 0, |
11196 | | 0, |
11197 | | 0, |
11198 | | 0, |
11199 | | { MVM_operand_write_reg | MVM_operand_num64, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11200 | | }, |
11201 | | { |
11202 | | MVM_OP_sp_deref_bind_i64, |
11203 | | "sp_deref_bind_i64", |
11204 | | ".s", |
11205 | | 3, |
11206 | | 0, |
11207 | | 0, |
11208 | | 0, |
11209 | | 0, |
11210 | | 0, |
11211 | | 0, |
11212 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_int64, MVM_operand_int16 } |
11213 | | }, |
11214 | | { |
11215 | | MVM_OP_sp_deref_bind_n, |
11216 | | "sp_deref_bind_n", |
11217 | | ".s", |
11218 | | 3, |
11219 | | 0, |
11220 | | 0, |
11221 | | 0, |
11222 | | 0, |
11223 | | 0, |
11224 | | 0, |
11225 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_num64, MVM_operand_int16 } |
11226 | | }, |
11227 | | { |
11228 | | MVM_OP_sp_getlexvia_o, |
11229 | | "sp_getlexvia_o", |
11230 | | ".s", |
11231 | | 4, |
11232 | | 1, |
11233 | | 0, |
11234 | | 0, |
11235 | | 0, |
11236 | | 0, |
11237 | | 0, |
11238 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_int16, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_obj } |
11239 | | }, |
11240 | | { |
11241 | | MVM_OP_sp_getlexvia_ins, |
11242 | | "sp_getlexvia_ins", |
11243 | | ".s", |
11244 | | 4, |
11245 | | 1, |
11246 | | 0, |
11247 | | 0, |
11248 | | 0, |
11249 | | 0, |
11250 | | 0, |
11251 | | { MVM_operand_write_reg | MVM_operand_type_var, MVM_operand_int16, MVM_operand_int16, MVM_operand_read_reg | MVM_operand_obj } |
11252 | | }, |
11253 | | { |
11254 | | MVM_OP_sp_getstringfrom, |
11255 | | "sp_getstringfrom", |
11256 | | ".s", |
11257 | | 3, |
11258 | | 1, |
11259 | | 0, |
11260 | | 0, |
11261 | | 0, |
11262 | | 0, |
11263 | | 0, |
11264 | | { MVM_operand_write_reg | MVM_operand_str, MVM_operand_spesh_slot, MVM_operand_int32 } |
11265 | | }, |
11266 | | { |
11267 | | MVM_OP_sp_getwvalfrom, |
11268 | | "sp_getwvalfrom", |
11269 | | ".s", |
11270 | | 3, |
11271 | | 1, |
11272 | | 0, |
11273 | | 0, |
11274 | | 0, |
11275 | | 0, |
11276 | | 0, |
11277 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_spesh_slot, MVM_operand_int64 } |
11278 | | }, |
11279 | | { |
11280 | | MVM_OP_sp_jit_enter, |
11281 | | "sp_jit_enter", |
11282 | | ".s", |
11283 | | 1, |
11284 | | 0, |
11285 | | 0, |
11286 | | 0, |
11287 | | 0, |
11288 | | 0, |
11289 | | 0, |
11290 | | { MVM_operand_write_reg | MVM_operand_obj } |
11291 | | }, |
11292 | | { |
11293 | | MVM_OP_sp_boolify_iter, |
11294 | | "sp_boolify_iter", |
11295 | | ".s", |
11296 | | 2, |
11297 | | 1, |
11298 | | 0, |
11299 | | 0, |
11300 | | 0, |
11301 | | 0, |
11302 | | 0, |
11303 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
11304 | | }, |
11305 | | { |
11306 | | MVM_OP_sp_boolify_iter_arr, |
11307 | | "sp_boolify_iter_arr", |
11308 | | ".s", |
11309 | | 2, |
11310 | | 1, |
11311 | | 0, |
11312 | | 0, |
11313 | | 0, |
11314 | | 0, |
11315 | | 0, |
11316 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
11317 | | }, |
11318 | | { |
11319 | | MVM_OP_sp_boolify_iter_hash, |
11320 | | "sp_boolify_iter_hash", |
11321 | | ".s", |
11322 | | 2, |
11323 | | 1, |
11324 | | 0, |
11325 | | 0, |
11326 | | 0, |
11327 | | 0, |
11328 | | 0, |
11329 | | { MVM_operand_write_reg | MVM_operand_int64, MVM_operand_read_reg | MVM_operand_obj } |
11330 | | }, |
11331 | | { |
11332 | | MVM_OP_sp_cas_o, |
11333 | | "sp_cas_o", |
11334 | | " ", |
11335 | | 4, |
11336 | | 0, |
11337 | | 0, |
11338 | | 0, |
11339 | | 0, |
11340 | | 1, |
11341 | | 0, |
11342 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
11343 | | }, |
11344 | | { |
11345 | | MVM_OP_sp_atomicload_o, |
11346 | | "sp_atomicload_o", |
11347 | | " ", |
11348 | | 2, |
11349 | | 0, |
11350 | | 0, |
11351 | | 0, |
11352 | | 0, |
11353 | | 0, |
11354 | | 0, |
11355 | | { MVM_operand_write_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
11356 | | }, |
11357 | | { |
11358 | | MVM_OP_sp_atomicstore_o, |
11359 | | "sp_atomicstore_o", |
11360 | | " ", |
11361 | | 2, |
11362 | | 0, |
11363 | | 0, |
11364 | | 0, |
11365 | | 0, |
11366 | | 1, |
11367 | | 0, |
11368 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_read_reg | MVM_operand_obj } |
11369 | | }, |
11370 | | { |
11371 | | MVM_OP_prof_enter, |
11372 | | "prof_enter", |
11373 | | ".s", |
11374 | | 0, |
11375 | | 0, |
11376 | | 0, |
11377 | | 0, |
11378 | | 0, |
11379 | | 0, |
11380 | | 0, |
11381 | | }, |
11382 | | { |
11383 | | MVM_OP_prof_enterspesh, |
11384 | | "prof_enterspesh", |
11385 | | ".s", |
11386 | | 0, |
11387 | | 0, |
11388 | | 0, |
11389 | | 0, |
11390 | | 0, |
11391 | | 0, |
11392 | | 0, |
11393 | | }, |
11394 | | { |
11395 | | MVM_OP_prof_enterinline, |
11396 | | "prof_enterinline", |
11397 | | ".s", |
11398 | | 1, |
11399 | | 0, |
11400 | | 0, |
11401 | | 0, |
11402 | | 0, |
11403 | | 0, |
11404 | | 0, |
11405 | | { MVM_operand_spesh_slot } |
11406 | | }, |
11407 | | { |
11408 | | MVM_OP_prof_enternative, |
11409 | | "prof_enternative", |
11410 | | ".s", |
11411 | | 1, |
11412 | | 0, |
11413 | | 0, |
11414 | | 0, |
11415 | | 0, |
11416 | | 0, |
11417 | | 0, |
11418 | | { MVM_operand_read_reg | MVM_operand_obj } |
11419 | | }, |
11420 | | { |
11421 | | MVM_OP_prof_exit, |
11422 | | "prof_exit", |
11423 | | " ", |
11424 | | 0, |
11425 | | 0, |
11426 | | 0, |
11427 | | 0, |
11428 | | 0, |
11429 | | 0, |
11430 | | 0, |
11431 | | }, |
11432 | | { |
11433 | | MVM_OP_prof_allocated, |
11434 | | "prof_allocated", |
11435 | | ".s", |
11436 | | 1, |
11437 | | 0, |
11438 | | 0, |
11439 | | 0, |
11440 | | 0, |
11441 | | 0, |
11442 | | 0, |
11443 | | { MVM_operand_read_reg | MVM_operand_obj } |
11444 | | }, |
11445 | | { |
11446 | | MVM_OP_ctw_check, |
11447 | | "ctw_check", |
11448 | | ".s", |
11449 | | 2, |
11450 | | 0, |
11451 | | 0, |
11452 | | 0, |
11453 | | 0, |
11454 | | 0, |
11455 | | 0, |
11456 | | { MVM_operand_read_reg | MVM_operand_obj, MVM_operand_int16 } |
11457 | | }, |
11458 | | { |
11459 | | MVM_OP_coverage_log, |
11460 | | "coverage_log", |
11461 | | ".s", |
11462 | | 4, |
11463 | | 0, |
11464 | | 0, |
11465 | | 0, |
11466 | | 0, |
11467 | | 0, |
11468 | | 0, |
11469 | | { MVM_operand_str, MVM_operand_int32, MVM_operand_int32, MVM_operand_int64 } |
11470 | | }, |
11471 | | { |
11472 | | MVM_OP_breakpoint, |
11473 | | "breakpoint", |
11474 | | ".s", |
11475 | | 2, |
11476 | | 0, |
11477 | | 0, |
11478 | | 0, |
11479 | | 0, |
11480 | | 0, |
11481 | | 0, |
11482 | | { MVM_operand_int32, MVM_operand_int32 } |
11483 | | }, |
11484 | | }; |
11485 | | |
11486 | | static const unsigned short MVM_op_counts = 884; |
11487 | | |
11488 | 15.0M | MVM_PUBLIC const MVMOpInfo * MVM_op_get_op(unsigned short op) { |
11489 | 15.0M | if (op >= MVM_op_counts) |
11490 | 0 | return NULL; |
11491 | 15.0M | return &MVM_op_infos[op]; |
11492 | 15.0M | } |